hw9bSol - CSE 260 Digital Computers: Organization and...

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- 1 - 1. (15 points) In the WashU-1 processor, the memory control signals and the address and data bus signals are defined by synchronous assignments (that is, the assignments fall within the scope of a synchronization condition). Rewrite the VHDL so that these signals are defined by asynchronous assignments (that is, outside the scope of any synchronization condition), but have essentially the same timing behavior as in the original version. Run the synthesizer on the new version of the WashU-1 to determine the number of flip flops and the maximum clock frequency. Compare these results to numbers reported for the original version. Discuss the differences you observe. Include a printout of your modified VHDL. For the original version of the processor, the synthesis report shows 328 flip flops and a minimum clock period of 97.7 MHz. The modified version shows 294 flip flops and a minimum clock period of 89.8 MHz. The difference in the number of flip flops is 34. This is exactly what one would expect, since we have eliminated the separate registers for aBus, dBus, en and rw. These signals have lengths of 16,16,1 and 1, a total of 34. The difference in clock frequency is roughly 9%, so the revised processor is that much slower than the original. For the implementation on the S3 board, this difference in performance is not important, but if we wanted the fastest possible version of the processor, we might prefer the original version to the revised one. The code that implements the revised version is shown below.
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This note was uploaded on 11/12/2010 for the course KTMT KTMT04 taught by Professor Son during the Spring '10 term at Dallas Colleges.

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hw9bSol - CSE 260 Digital Computers: Organization and...

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