hw10_2 - using 5 block RAMs. You may use more than one...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
- 1 - 1. (10 points) Consider a 32Kx32 SRAM (K means 1024). How many address bits does this memory require? Assuming that the central memory array has the same number of rows as it has columns, how many rows are there? How many of the address bits are used by the row decoder? How many by the column decoder? In what row and what column of the memory would you find bit 2 of the word with address 54d2? Assume that the row decoder uses the high order address bits and that the column decoder uses the low order address bits. 2. (10 points) The block RAMS on the FPGA used on the S3 board have 16,384 bits and can be configured in a variety of ways. The configurations include 512x32, 1024x16, 2048x8, 4096x4, 8192x2, 16384x1. Draw a diagram showing how you can implement a 6144x12 bit memory
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: using 5 block RAMs. You may use more than one distinct configuration, but make sure that you label each block RAM you use and show how the address and data lines of the different block RAMs are connected to implement the overall memory. Assume that each block RAM has an enable input, a read/write input, a data input and a data output. You may assume that the data outputs have internal tristate buffers that are turned off when the enable input is low. If you need to use any external decoders, make sure that you show how they connect to the address inputs and the address lines of the individual block RAMs. CSE 260 Digital Computers: Organization and Logical Design Homework 10 Jon Turner Due 4/8/2008...
View Full Document

This note was uploaded on 11/12/2010 for the course KTMT KTMT04 taught by Professor Son during the Spring '10 term at Dallas Colleges.

Ask a homework question - tutors are online