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Unformatted text preview: CSE 260 Digital Computers: Organization and Logical Design Homework 13 Solutions
Jon Turner April 22, 2008 1. (15 points) The logic diagram below shows an 8 bit ripple-borrow decrement circuit. Draw a logic diagram for an 8 bit borrow-lookahead decrement circuit, similar to the carrylookahead increment circuit on page 13-17 of the notes. What is the worst-case propagation delay for your circuit, if all gates have a delay of 1 ns? What is the worst-case propagation delay for a 32 bit version of the circuit? How does this compare to a 32 bit version of the ripple-borrow circuit? The lookahead version is shown below. The worst-case propagation delay is 5 ns. A 32 bit version has a worst-case propagation delay of 7 ns. This compares to 33 ns for the ripple-carry version. X7 X6 X5 X4 X3 X2 X1 X0 decrement D7 D6 D5 D4 D3 D2 D1 D0 X7 X6 X5 X4 X3 X2 X1 X0 decrement D7 D6 D5 D4 D3 D2 D1 D0 -1- 2. (10 points) We can define a comparison circuit based on the following observation. ai . . . a0 > bi . . . b0 if and only if ai>bi or (ai=bi and ai1 . . . a0 > bi1 . . . b0) Draw a schematic of a four bit comparison circuit made from four identical elements connected in a linear arrangement, based on this observation. A3 A2 A1 A0 A>B B3 B2 B1 B0 -2- ...
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This note was uploaded on 11/12/2010 for the course KTMT KTMT04 taught by Professor Son during the Spring '10 term at Dallas Colleges.
- Spring '10