Unformatted text preview: then use the inAck signal to inform the client when the insert has been done. Similarly, if the delete input goes high while an insert is in progress, the circuit should remember that a delete is to be done, and proceed with it after completing the insert. The circuit may ignore a new insert request while it is doing an insert, and may ignore a new delete request while it is doing a delete. If the circuit is idle and gets simultaneous requests to insert and delete, it should do the delete first, then the insert. Write a VHDL architecture to implement this version of the priority queue. You are not required to simulate it. Hint: consider using thee separate processes: one for the input interface, one for the output interface and a third for the two arrays of records. CSE 260 Digital Computers: Organization and Logical Design Homework 7 Jon Turner 10/21/2010...
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This note was uploaded on 11/12/2010 for the course KTMT KTMT04 taught by Professor Son during the Spring '10 term at Dallas Colleges.
- Spring '10