hw7 - then use the inAck signal to inform the client when...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
- 1 - 1. (20 points) In this problem, you are to modify the priority queue module described in the lecture notes. This version will have two logically separate interfaces, one for inserting items into the priority queue and another for removing items. Use the following entity declaration. entity priQueue is port( clk, reset : in std_logic; -- input interface insert: in std_logic; key, value : in word; inAck, full: out std_logic; -- output interface delete: in std_logic; smallValue : out word; outAck, empty : out std_logic); end priQueue; Note that the busy output has been replaced with two acknowledgement outputs inAck and outAck . In this version, the completion of an insert or delete operation is indicated by raising the inAck or outAck output for one clock tick. If the insert input is raised high while a delete operation is in progress, the circuit should store the key and value inputs in a register and then perform the insert operation as soon as the delete operation is completed,
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: then use the inAck signal to inform the client when the insert has been done. Similarly, if the delete input goes high while an insert is in progress, the circuit should remember that a delete is to be done, and proceed with it after completing the insert. The circuit may ignore a new insert request while it is doing an insert, and may ignore a new delete request while it is doing a delete. If the circuit is idle and gets simultaneous requests to insert and delete, it should do the delete first, then the insert. Write a VHDL architecture to implement this version of the priority queue. You are not required to simulate it. Hint: consider using thee separate processes: one for the input interface, one for the output interface and a third for the two arrays of records. CSE 260 Digital Computers: Organization and Logical Design Homework 7 Jon Turner 10/21/2010...
View Full Document

This note was uploaded on 11/12/2010 for the course KTMT KTMT04 taught by Professor Son during the Spring '10 term at Dallas Colleges.

Ask a homework question - tutors are online