Hw3 - a: in std_logic_vector(2 to 0); b,c,d: in...

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- 1 - CSE 260 Homework 3 Due September 15, 2009 1. (10 points) Rewrite the following VHDL module using only ordinary signal assignments (no conditional assignments). entity foo is port( a,b,c,d: in std_logic; x: out std_logic; y: out std_logic_vector (1 downto 0); end entity foo; architecture arch of foo begin x <= b and c when a = „0‟ else not c when a>b else a or d; y <= (a & d) when a = „1‟ else (b & (not c)) when (b=„0‟ and c=„1‟) else „1‟ & c; end arch; 2. (10 points) Draw a circuit corresponding to the following VHDL module. Just use a block called “adder” for any addition that’s done. entity foo is port(
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Unformatted text preview: a: in std_logic_vector(2 to 0); b,c,d: in std_logic_vector(3 downto 0); x,y: out std_logic_vector(3 downto 0)); end entity foo; architecture arch of foo signal z: std_logic_vector(3 downto 0); begin z &lt;= b xor c; with a select x &lt;= z when 000, c when 001 | 100, d when 110 | 111 | 101, b+c when 0 1 1, c+d when others; y &lt;= c+d when a = 010 else d when a &gt;= 101 and a &lt;= 111 else z when a = 000 else b+c when a = 011 else c when others; end arch; 3. (10 points) Rewrite the VHDL module in the previous problem using a process block and an if-then-else statement....
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