project35_final_paper (1)

# project35_final_paper (1) - ARITHMETIC LOGIC UNIT (ALU) and...

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ARITHMETIC LOGIC UNIT (ALU) and BOOTH’S MULTIPLIER FOR AMR7 MICROPROCESSOR By Tam Nguyen and Long Pham ECE 345 T.A: Jon Benson Date: 4/29/2000 Project Number: 35

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ABSTRACT There are three major designs mentioned in this paper. First, the arithmetic logic unit (ALU) is designed to support for every conditional instruction in 32-bits ARM7 microprocessor. Two major tasks of ALU are to generate the result for arithmetic/logic operations and to generate the conditional signals. The functionalities of ALU consist of move, pass, add, add carry, subtract, subtract carry, bit-wise OR, bit-wise AND, bit-wise XOR, and bit-wise AND NOT . The adder in ALU is implemented by using a Carry Select Adder. Second, the multiplier, which supports for multi-cycle multiply instruction in ARM7, is designed by using Booth’s algorithm. Finally, the voltage regulator is designed to meet some specifications (output voltage’s tolerance, output current’s delivering, and input’s polarity). ii
TABLE OF CONTENTS PAGE 1. INTRODUCTION 1 1.0 Introduction 1 1.1 Description of Booth’s multiplier 2 1.2 Description of ALU 2 1.3 Description of Voltage Regulator 3 2. DESIGN PROCEDURE 4 2.1 Booth’s multiplier 4 2.2 ALU 4 2.3 Voltage Regulator 6 3. DESIGN DETAILS 7 3.1 Booth’s multiplier 7 3.2 ALU 8 3.3 Voltage Regulator 9 4. DESIGN VERIFICATION 10 4.1 Booth’s multiplier 10 4.2 ALU 10 4.3 Voltage Regulator 11 5. COSTS 12 5.1 Booth’s multiplier and ALU 12 5.2 Voltage Regulator 12 6. CONSCLUSION 13 iii

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1. INTRODUCTION 1.0 Introduction The high-level block diagram of 32-bit ARM7 microprocessor is shown in Figure.1 below. This processor will support 11 instructions: Data Processing Transfer, Multiply, Single Data Swap, Single Data Transfer, Undefined, Block Data Transfer, Branch, Coproc Data Transfer, Coproc Data Operation, Coproc ResigterTransfer, and Software interrupt . Our task is to design and implement the ALU and the Multiplier module to chip level by using synthesis tool (Synopsys with 0.25 μ , 3.3V technology). Others will design the rest of the processor. Fig.1. High-level block of ARM7 1.1 Description of Booth’s multiplier: Address Register Address Incrementer Register Bank (31x32bit registers) (6 status registers) Booth’s Multiplier Barrel Shifter 32-bit Write Data Register Instruction Pipeline & Read Data Register Instruction Decoder Control Logic 1
The multiplier module takes inputs A, B (32-bits), Enable and System clock (Sysclk). This module will give the least significant 32 bits of the product of two 32-bit operands, and Ready. Enable signal tells when multiplying begins, and Ready signal tells when multiplying ends. The result of a signed multiply and of an unsigned multiply of 32-bit operands differ only in the upper 32 bits, the low 32 bits of the signed or unsigned result are identical. So, they can use for both signed and unsigned multiplies. Block Diagram of Booth’s Multiplier:

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## This note was uploaded on 11/15/2010 for the course ECE 1234 taught by Professor G.wdwdw during the Spring '10 term at St. Johns Seminary.

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project35_final_paper (1) - ARITHMETIC LOGIC UNIT (ALU) and...

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