hw2_soln_Sp2010

Hw2_soln_Sp2010 - ECE 561(Sp 2010 Homework#2 Solutions 1 Problem 8.13 The counting direction is controlled by QD count up when QD=1 count down when

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ECE 561 (Sp 2010) Homework #2 – Solutions 1. Problem 8.13. The counting direction is controlled by QD: count up when QD=1, count down when QD=0. A load occurs when the counter is in the terminal state: 1111 when counting up, 0000 when counting down. The MSB is complemented during a load and the other bits are unchanged. Let us assume that the counter is initially in one of the states 0000-0111. Then the counter counts down (QD=0). Upon reaching state 0000, it loads 1000 and subsequently counts up (QD=1). Upon reaching state 1111, the counter loads 0111, and subsequently counts down, repeating the cycle. If the counter is initially in one of the states 1000-1111, the same cyclic behavior is observed. The counting sequence has a period of 16 and is, in decimal: 8,9,10,11,12,13,14,15,7,6,5,4,3,2,1,0,8,9,. .. If only the three LSBs are observed, the sequence is: 0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0,0,1,. ..
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This note was uploaded on 11/15/2010 for the course ECE 561 taught by Professor Orin,d during the Spring '08 term at Ohio State.

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Hw2_soln_Sp2010 - ECE 561(Sp 2010 Homework#2 Solutions 1 Problem 8.13 The counting direction is controlled by QD count up when QD=1 count down when

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