ECE 561 (Sp 2010)
Homework #2 – Solutions
1. Problem 8.13.
The counting direction is controlled by QD: count up when QD=1, count down when QD=0.
A load occurs when the counter is in the terminal state: 1111 when counting up, 0000 when
counting down. The MSB is complemented during a load and the other bits are unchanged.
Let us assume that the counter is initially in one of the states 0000-0111. Then the counter
counts down (QD=0). Upon reaching state 0000, it loads 1000 and subsequently counts up
(QD=1). Upon reaching state 1111, the counter loads 0111, and subsequently counts down,
repeating the cycle.
If the counter is initially in one of the states 1000-1111, the same cyclic behavior is observed.
The counting sequence has a period of 16 and is, in decimal:
If only the three LSBs are observed, the sequence is: