hw2-Sp2010

hw2-Sp2010 - ECE561: Digital Circuit Design Sp 2010...

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ECE561: Digital Circuit Design Sp 2010 Homework #2 1. Problem 8.13. Note that 74x169 loads 4 bit data when LD is asserted. If LD is negated and both of ENP and ENT are asserted, 74x169 counts up when UP/DN is 1 and counts down when UP/DN is 0. RCO has the following function: ) QA QB QC QD UP/DN QA QB QC QD (UP/DN ENT RCO 2. Design a modulo-112 counter with CLR_L input that counts from 0 to 111 using two 74x163s and one 74x138. 3. We have two controller chips for two peripheral devices each of which has an enable input EN_L and 3 address lines (A2, A1, A0) to address 8 ports in it. Suppose that we want to map the 8 ports of the first device to the I/O mapped addresses from 10010000 to 10010111 and second device to the addresses from 10011000 to 10011111. How can we connect 8 bit address bus from the microprocessor to EN_L and A2, A1, A0 of the two peripherals? Use 74x138 and a couple of inverters if necessary. 4. (a) Use the three-step approach to analyze the following figure. Note that only two bits of the counter are used. Be sure to finish with a state diagram with all inputs and outputs clearly
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This note was uploaded on 11/15/2010 for the course ECE 561 taught by Professor Orin,d during the Spring '08 term at Ohio State.

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hw2-Sp2010 - ECE561: Digital Circuit Design Sp 2010...

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