hw3-Sp2010

hw3-Sp2010 - register: Two-Bit Shift Register : t s S 1 , S...

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1 ECE561: Digital Circuit Design Spring 2010 Homework #3 1. Problem 7.44. Assume that once INIT is negated, it will not be asserted again until sometime after Z goes to a 1. 2. (a) Use the 9-step design approach to design a 2-bit version of the 74LS194 with NAND gates ('LS00, 'LS10, ….), inverters ('LS04), and D flip/flops (74LS74). You need not provide a state diagram in this case but be sure to finish with a complete logic diagram. Use the following block diagram: (b) Use the timing specifications from Table 6-2 in the text (``Maximum'' values) for the gates and from Table 8-1 for the 74LS74 to provide similar specifications for the 2-bit shift
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Unformatted text preview: register: Two-Bit Shift Register : t s S 1 , S B, A RIN, LIN t h S 1 , S B, A RIN, LIN CLR Q CLK Q f MAX (c) By inspecting the results of Part (a), give the equations for D A , D B , D C , D D for a 4-bit version, that is for the 74LS194. 2 3. Problem 7.60. 4. Using a 74LS194, design a sequence generator which cycles through the following sequence (top to bottom and back again): 1100 0110 1101 1011 0111 0011 0001 0000 1000 Have all unused states reset to 0000 (synchronously)....
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This note was uploaded on 11/15/2010 for the course ECE 561 taught by Professor Orin,d during the Spring '08 term at Ohio State.

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hw3-Sp2010 - register: Two-Bit Shift Register : t s S 1 , S...

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