hw4_soln_Sp2010

# hw4_soln_Sp2010 - ECE 561 Homework#4 – Solutions 1...

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Unformatted text preview: ECE 561 Homework #4 – Solutions 1. Problem 1: Seven-segment decoder library IEEE; use IEEE.std_logic_1164.all; entity V74x49b is port ( D: in STD_LOGIC; C: in STD_LOGIC; B: in STD_LOGIC; A: in STD_LOGIC; BI_L: in STD_LOGIC; ENHEX, ERRDET: in STD_LOGIC; S_L: out STD_LOGIC_VECTOR (6 downto 0) ); end V74x49b; architecture V74x49b_arch of V74x49b is signal I: STD_LOGIC_VECTOR (3 downto 0); signal BI, S: STD_LOGIC; begin I <= D & C & B & A; BI <= not BI_L; S_L <= not S; process(BI,I) begin if BI=’0’ and ENHEX=’0’ then case I is when "0000" => S <= "1110111"; when "0001" => S <= "0010010"; when "0010" => S <= "1011101"; when "0011" => S <= "1011011"; when "0100" => S <= "0111010"; when "0101" => S <= "1101011"; when "0110" => S <= "0101111"; when "0111" => S <= "1010010"; when "1000" => S <= "1111111"; when "1001" => S <= "1111010"; when others => S <= "0000000"; end case; elsif ENHEX=’1’ and ERRDET = ’0’ then case I is when "0000" => S <= "1110111"; when "0001" => S <= "0010010";...
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hw4_soln_Sp2010 - ECE 561 Homework#4 – Solutions 1...

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