hw5_soln_Sp2010

hw5_soln_Sp2010 - like 111 010 000. The Y2_L output will...

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1 ECE561: Digital Circuit Design Spring 2010 Homework #5 - Solutions 1. The path from the Q2 counter output (B decoder input) to the Y2_L output has 10 ns more delay than the Q3 and Q1 (C and A) paths. Let us examine the possible Y2_L glitches in Figure 8–43 with this in mind: a. 3 4 (011 100) Because of the delay in the Q2 path, this transition will actually look like 011 110 100. The Y6_L output will have a 10-ns glitch, but Y2_L will not. b. 7 0 (111 000) Because of the delay in the Q2 path, this transition will actually look
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Unformatted text preview: like 111 010 000. The Y2_L output will have a 10-ns glitch, but the others will not. G1 G2A-L G2B-L Y2_L Y3_L Y4_L Y5_L Y6_L Y7_L Y1_L Y0_L A B C Q1 Q2 Q3 2 2. The state assignment below will avoid the output glitch problem for the following state diagram. a b c f - e d - In the state assignment map the next state in the state diagram is always adjacent to the present state. 3. The state diagram given in Problem 2 is a solution of this problem, but you may use fewer states for this problem....
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hw5_soln_Sp2010 - like 111 010 000. The Y2_L output will...

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