hw6_soln_Sp2010

# hw6_soln_Sp2010 - 1 1 0 1 0 0 0 1 0 1 1 0 1 1 0 0 1 1 1 1 0...

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1 ECE 561 Sp 2010 Homework #6 - Solutions 1. Use GAL22V10R with the following pin selections. Inside the GAL22V10R chip, the following connections should be made: ) 0 1 0 1 0 1 0 1 ( B S S Qc S S Qa S S Qb S S CLR D b + + + = ) 0 1 0 1 0 1 0 1 ( C S S Qd S S Qb S S Qc S S CLR D c + + + = ………… ) 0 1 0 1 0 1 0 1 ( H S S LIN S S Qc S S Qh S S CLR D h + + + = RIN A B C D E F G H LIN S1 CLK I1/CLK I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 Qa Qb Qc Qd Qe Qf Qg Qh CLR_L S0 ) 0 1 0 1 0 1 0 1 ( A S S Qb S S RIN S S Qa S S CLR D a + + + =

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2 2. Let the two inputs be A=A 3 A 2 A 1 A 0 and B=B 3 B 2 B 1 B 0 . Then A 1 A 0 and B 1 B 0 are connected to function generator F which is programmed in the following way: A 1 A 0 B 1 B 0 F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0
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Unformatted text preview: 1 1 0 1 0 0 0 1 0 1 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 Funcation generator G should be organized in the same way as F for A 3 A 2 and for B 3 B 2 . Then funcation generator H can be organized as (H1 is cascaded from the other equilty checker) * If only for the two inputs, it should be 1. F G H 1 H 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0* 1 1 1 1...
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hw6_soln_Sp2010 - 1 1 0 1 0 0 0 1 0 1 1 0 1 1 0 0 1 1 1 1 0...

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