Lecture17_19Updated-05122010

Lecture17_19Updated-05122010 - 4-bit Serial Adder...

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4-bit Serial Adder ecomposing state machines, synchronous design (Decomposing state machines, synchronous design methodology, system controller design, ynchronous inputs and output glitches asynchronous inputs and output glitches ) ead: 7.8 (pg. 587- 88), .7.1, 7.1.3, Read: 7.8 (pg. 587 588), 8.7.1, 7.1.3, 8.4.4, 8.8.3
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Review of Combinational Adders 1-bit full adder and 4-bit ripple adder
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Review of Binary Serial Adder • Serial input feed (two data streams A and B) Generate serial output A S CLR HOLD CLR – clear the previous carry synchronously HOLD – hold the previous value of the carry i B i i Carry
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esign Example Using Adder Chips Design Example Using Adder Chips • LS183: dual 1 bit full adders carry A B0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 Q(Carry) 0 0 S 01 0 1
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roblem Statement Problem Statement esign a 4- it adder based on a serial approach Design a 4 bit adder based on a serial approach – Parallel feed of X 1 and X 2 – Parallel out of Y comes out after few cycles START may be long (External guy will –F inal carry available X 1 X 2 negate START only after detecting DONE) TART 44 ONE 4-bit adder START CONTROL DONE ONTROL=1 X lus X Y 4 CONTROL=1, X 1 plus X 2 -> Y CONTROL=0, X 1 plus Y -> Y Y CARRY
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Start from LBB (Logic Building Block) • Here, we have some basic building blocks in mind – 4-bit shift registers, binary serial adder, etc • Tie these elements together and make them controllable om the outside world from the outside world • We want to take maximum advantage of common building locks (MSI chips that are available) blocks (MSI chips that are available)
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Design System Architecture First step: divide the system into a control unit and data unit Data unit – stores, routes, combines, and generally process data – Control unit – starting & stopping the process, testing conditions, and deciding what to do next
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Data Unit & Control Unit X 1 X 2 hift register hift register 4 4 4 Y Shift register Shift register Binary START ONTROL arry serial adder Control Unit Data Unit CONTROL Carry DONE
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Architecture ABCD RIN LIN S S X1 1 0 Q A Q B Q C Q D CLR
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This note was uploaded on 11/15/2010 for the course ECE 561 taught by Professor Orin,d during the Spring '08 term at Ohio State.

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Lecture17_19Updated-05122010 - 4-bit Serial Adder...

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