MidTerm1Review-Sp2010

MidTerm1Review-Sp201 - Midterm 1 Review Topics(1 Three step analysis(Equations/State Table/State Diagram From the logic circuit to state diagram th

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
Midterm 1 Review
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Topics (1) • Three step analysis (Equations/State Table/State Diagram) – From the logic circuit to state diagram • Usage of MSI chips ounters (cascading modulo counter etc ) – Counters (cascading, modulo counter, etc.) – Shift registers – Decoders • Max frequency, setup and hold times, propagation delay – Caused by the delays of flips/flops and gates – When use the max and when min delays
Background image of page 2
Topics (2) • 2’s complement system
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 4
Background image of page 5
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 11/15/2010 for the course ECE 561 taught by Professor Orin,d during the Spring '08 term at Ohio State.

Page1 / 5

MidTerm1Review-Sp201 - Midterm 1 Review Topics(1 Three step analysis(Equations/State Table/State Diagram From the logic circuit to state diagram th

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online