Unformatted text preview: 284 Circuit Simplification; The Karnaugh Map is required. We will see later that equivalent gates
and available gate types will be a determining
factor of which function is actually used. T_he co_1_np_lement_ functicin for Example 3 is E =
(A+B)(A+B+D)(A+B+C+D) and is mapped in Fig.
288. The resulting function is E=(A+B)(A+D)(A+C). To
obtain F, =E=(A+B)(A+C)(A+D) =A+B + A+C + A+D
=A§+AE+A5 =A(§+E+ﬁ) In some cases, there are more terms in a sum of the
products function requiring a 1 output than a 0
output as will be shown in Example 4; this could
also occur for a product of the sums function.
Example 4.
F=ABC+AEC+ABC+KEC+KFC
The Karnaugh maps for F and F are shown in
Fig. 289 (:1) and (b), respectively. After mapping
the one terms, the result is F=KE+AG+BG+EG
After mapping the zero terms, the result is
E=AFG+BG The results of the one terms and zero
terms mapping are equivalent since F=AEG+BC=
(A+B+C)(§+O)=AF+AO+BG+FC. Mapping the zero
terms thus results in a simpler, but complement,
function. Complementing this function will lead to
a simpler circuit giving the same result as the
original function. Notice that complementing E
to give the function F led directly to a circuit using NOR gates. The NAND gate will result if the same
procedure is used for a product of the sum function. We will implement these circuits in our exercise procedure to show that the same output results
will be obtained. Fig. 289 Equipment and Materials The Model A818145 Digital Logic Trainer with:  2input AND Gates (7408)  2input OR Gates (7432)  2input NAND Gates (7400)
 2input NOR Gates (7402)
4input NAND Gates (7420)
 Hex Inverters (7404)  Switches  LED Displays Additional Reading See bibliography at the back of this manual for
additional reading material on Boolean algebra,
Karnaugh maps and logic simpliﬁcation techniques.
Review the materials contained in preceding ex
ercises on logic gates and Boolean algebra. CDCDerFDJWOJrP
I Objective A. Use a Karnaugh map and dual gate
concept to design, implement and verify 3 VOTE
SYSTEM that will indicate a majority “YES”,
majority “NO” and a “TIE” vote. Preparatory Information. We will simplify and
implement the vote system of the preceding ex
ercise but now use the Karnaugh map to simplify
the functions. We will also use DeMorgan’s theorem
to implement the circuit with dual or equivalent
gates. Typically, a design is started by listing all of the
output requirements 1n terms of the i_nput variables.
In this prob__lem they were, X= ABCD+ABCD+
ABCD+§§QQ+é§9D= 1__fo_r a eaoﬁu_:YES”
vote, Y=ABCD+ABCD+ABCD+ABCD+ABCD= —1 for
a majority “NO” vote, and Z equals the remaining
terms that would indicate a tie, or XY. Now we
will simplify the functions for X and Y, using the Karnaugh map. FX =KBCD+A§CD+ABED+ABcﬁ+ABCD The simplified expression for X from the Karnaugh
map shown in Fig. 2810 contains four terms,
each with one variable eliminated. The function
for X is Fx =ABC+ABD+ACD+BCD. This can be
factored to give FX=AB(C+D)+CD(A+B). Both ...
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 Fall '05
 Myer,B

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