10.1.1.85.4891 - Pseudorandom,Weighted Random and...

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Unformatted text preview: Pseudorandom,Weighted Random and Pseudoexhaustive Test Patterns Generated in Universal Cellular Automata Ondrej Novak Technical University Liberec, Hálkova 6, 461 17 Liberec I, Czech Republic tel.: + 420 48 53553460, fax: + 420 48 5353112 e-mail: [email protected] Abstract. The paper presents a design method for Built-In Self Test (BIST) that uses a cellular automaton (CA) for test pattern generation. We have extensively studied the quality of generated patterns and we have found several interesting properties of them. The first possibility how to use the CA is to generate pseudoexhaustive test sets as the CA can generate code words of codes with higher minimal code distance of the dual code. There is no need of reseeding the CA in order to generate all the code words. This type of test set can be advantageously used for testing with low number of inputs and low size of cones in the circuits under test (CUT). The proposed CA can also generate weighted random patterns with different global weights which can be used instead of linear feedback shift register (LFSR) pseudorandom sequences, the fault coverage is higher. It can also be used as deterministic pattern compactor in mixed mode testing. The generated sequence can be also easily used for testing CUTs with input-oriented weighted random patterns. The CA is formed by T flip-flops and does not contain any additional logic in the feedback. We proposed a new scheme of BIST where the CA is a part of a modified scan chain. Several experiments were done with ISCAS 85 and 89 benchmark circuits. We compared the quality of the generated test patterns with the quality of the patterns generated in an LFSR . Key words : Cellular automata, BIST, linear cyclic codes, linear feedback shift registers, hardware test pattern generators, weighted random testing, pseudoexhaustive testing 1 Introduction Built-in self-test (BIST) is a concept useful for testing the VLSI circuits, where it solves the problem of limited access to the circuit-under-test (CUT), offers on-line and in-line applicability of the test sets and very radically reduces the amount of output information - see e.g. [16 ]. To implement BIST, we must embed both the test pattern generator (TPG) and output data compactor into the structure of the CUT which naturally imposes limits on their size, complexity and level of control which may lead to a loss of fault coverage. Our task was to find BIST structures and their function algorithms, which will guarantee the required level of fault coverage when observing the simplicity requirements. The techniques for hardware test pattern generation can be classified in the following groups: pseudoexhaustive testing [22] , pseudorandom testing [1], weighted random testing [22] , deterministic tests [5] and mixed mode pattern generation [13], [12]....
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This note was uploaded on 11/18/2010 for the course ECE 271 taught by Professor Garrisongreenwood during the Spring '10 term at Pohang University of Science and Technology.

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10.1.1.85.4891 - Pseudorandom,Weighted Random and...

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