Lesson-40 - Module 8 Testing of Embedded System Version 2...

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Unformatted text preview: Module 8 Testing of Embedded System Version 2 EE IIT, Kharagpur 1 Lesson 40 Built-In-Self-Test (BIST) for Embedded Systems Version 2 EE IIT, Kharagpur 2 Instructional Objectives After going through this lesson the student would be able to • Explain the meaning of the term ‘Built-in Self-Test (BIST)’ • Identify the main components of BIST functionality • Describe the various methods of test pattern generation for designing embedded systems with BIST • Define what is a Signature Analysis Register and describe some methods to designing such units • Explain what is a Built-in Logic Block Observer (BILBO) and describe how to use this block for designing BIST Built-In-Self-Test (BIST) for Embedded Systems 1. Introduction BIST is a design-for-testability technique that places the testing functions physically with the circuit under test (CUT), as illustrated in Figure 40.1 [1]. The basic BIST architecture requires the addition of three hardware blocks to a digital circuit: a test pattern generator, a response analyzer, and a test controller. The test pattern generator generates the test patterns for the CUT. Examples of pattern generators are a ROM with stored patterns, a counter, and a linear feedback shift register (LFSR). A typical response analyzer is a comparator with stored responses or an LFSR used as a signature analyzer. It compacts and analyzes the test responses to determine correctness of the CUT. A test control block is necessary to activate the test and analyze the responses. However, in general, several test-related functions can be executed through a test controller circuit. Hard ware pattern generator M U X CUT Test Controller ROM Output Response Compactor Comparator Test PO Signature Good/Faulty Reference Signature Fig. 40.1 A Typical BIST Architecture As shown in Figure 40.1, the wires from primary inputs (PIs) to MUX and wires from circuit output to primary outputs (POs) cannot be tested by BIST. In normal operation, the CUT receives its inputs from other modules and performs the function for which it was designed. During test mode, a test pattern generator circuit applies a sequence of test patterns to the CUT, Version 2 EE IIT, Kharagpur 3 and the test responses are evaluated by a output response compactor. In the most common type of BIST, test responses are compacted in output response compactor to form (fault) signatures . The response signatures are compared with reference golden signatures generated or stored on- chip, and the error signal indicates whether chip is good or faulty. Four primary parameters must be considered in developing a BIST methodology for embedded systems; these correspond with the design parameters for on-line testing techniques discussed in earlier chapter [2]....
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This note was uploaded on 11/18/2010 for the course ECE 12345 taught by Professor Garrisongreenwood during the Spring '10 term at Pohang University of Science and Technology.

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Lesson-40 - Module 8 Testing of Embedded System Version 2...

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