Lec-13-HDL - Hardware Description Languages Describe...

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CS 150 - Fall 2000 - Hardware Description Languages - 1 Hardware Description Languages Describe hardware at varying levels of abstraction Structural description Textual replacement for schematic Hierarchical composition of modules from primitives Behavioral/functional description Describe what module does, not how Synthesis generates circuit for module Simulation semantics
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CS 150 - Fall 2000 - Hardware Description Languages - 2 HDLs Abel (circa 1983) - developed by Data-I/O Targeted to programmable logic devices Not good for much more than state machines ISP (circa 1977) - research project at CMU Simulation, but no synthesis Verilog (circa 1985) - developed by Gateway (absorbed by Cadence) Similar to Pascal and C Delays is only interaction with simulator Fairly efficient and easy to write IEEE standard VHDL (circa 1987) - DoD sponsored standard Similar to Ada (emphasis on re-use and maintainability) Simulation semantics visible Very general but verbose IEEE standard
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CS 150 - Fall 2000 - Hardware Description Languages - 3 Verilog Supports structural and behavioral descriptions Structural Explicit structure of the circuit E.g., each logic gate instantiated and connected to others Behavioral Program describes input/output behavior of circuit Many structural implementations could have same behavior E.g., different implementation of one Boolean function We’ll only be using behavioral Verilog in DesignWorks Rely on schematic when we want structural descriptions
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CS 150 - Fall 2000 - Hardware Description Languages - 4 module xor_gate (out, a, b); input a, b; output out; wire abar, bbar, t1, t2; inverter invA (abar, a); inverter invB (bbar, b); and_gate and1 (t1, a, bbar); and_gate and2 (t2, b, abar); or_gate or1 (out, t1, t2); endmodule Structural Model
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CS 150 - Fall 2000 - Hardware Description Languages - 5 module xor_gate (out, a, b); input a, b; output out; reg out; assign #6 out = a ^ b; endmodule Simple behavioral model Continuous assignment delay from input change to output change simulation register - keeps  track of value of signal
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CS 150 - Fall 2000 - Hardware Description Languages - 6 module xor_gate (out, a, b); input a, b; output out; reg out; always @(a or b) begin #6 out = a ^ b; end endmodule Simple Behavioral Model always block specifies when block is executed  I.e., triggered by which signals
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Lec-13-HDL - Hardware Description Languages Describe...

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