Unformatted text preview: The Decoder 6-5 W INVERTER (D) defective, always at a
1 level output.
Gate (7) defective, always at a 1 level output.
Gate (7) defective, always at a 0 level output. 4. The line identification AT B‘c" at the output
of gate (D) of Fig. 6-3 means: 8.. b. NOT A AND NOT B AND NOT C are
all 0 when the decoder zero output is 1.
The input code is K B— G and gate (D)
performs the NAND operation. The inputs to gate (D) are LO when
the decoder zero output is HI. There is no need for the INVERTER (H) because gate (D) performs the AND
operation. 5. If the inputs to gate (G) in Fig. 6-3 are
Checked and the results of Table 6-5 are
observed, which circuit component is most
likely defective? BCD INPUTS GATE G INPUTS a.
d c E A
l—‘OO—‘Or—JOHO Table 6-5 (A).
(C). None. 6. Gate (K) in Fig. 6-3 performs what logic operation: a NOR.
c. OR. d NOT. Optional Test Exercise 1. Can any of the input lines to the AND gates shown in Fig. 6-2 be permanently tied to a
logic 1 line and have the decoder provide the
proper outputs? ...
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- Fall '05