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Electronic Labs_97

# Electronic Labs_97 - I IIIIIIIIII IIIIIIIII IIIIIIIII...

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Unformatted text preview: I IIIIIIIIII IIIIIIIII IIIIIIIII IIIIIIII IIIIIIII IIIIIIIII IIIIIIIII IIIIIIIIII IIIIIIIII IIIIIIIIII IIIIIIIII Table 7-4 is checked for errors. Here, in a data transmission system, the data word is received and fed to a parity-bit detector circuit. The parity-bit detector circuit compares the bits in the 4-bit data word and determines if the data word is odd or even. It then compares the parity-bit to the word in- formation and generates an error output if they are not consistent (in which case the receiver would automatically signal the transmitter to retransmit the data word before proceeding to transmit the next data word). RECEIVED WORD FREIM SWITCHES PARITY-BIT DETECTOR Exclusive—OR/NOR Gates; Parity Circuits 7-5 A parity-bit detector circuit is shown in Fig. 7-6. Gates (A), (B) and (C) compare the data part of ' the received word to determine if it has an odd or even number of bits. Since it uses EXCLUSIVE- NOR gates it will have a 0 output for an odd num- ber of data bits. The data detector output is then compared to the received parity-bit by an EX- CLUSIVE-OR gate (D). If the two inputs to gate (D) are not the same the output of gate D is 1, indicating that an error exists. Exercise Procedure [I 4.a)Add a remaining AND/OR/INVERT gate to the parity-bit circuit constructed in the preceding procedure to make the parity-bit de- tector shown in Fig. 7—6. Use a NOR gate (7402) for the three inverters. [I b) Turn on the trainer power. El c)Complete Table 7-5 on the following page for the RECEIVED WORD combinations shown. The completed truth table should indicate the operation of an odd-bit type parity-bit detector circuit; that if the received word has an odd number of bits and the parity bit is 0, the error output is 0 indicating that the data word received is correct. If the error output is 1 it indicates an error exists in the data word received. I] d)Do not disassemble this circuit as it will be used in the next procedure. Objective D. Analyze the possible trouble symp- toms in a parity-bit error-checking system by verifying the absence of proper states. Preparatory Information. An error indication in the parity-bit system often indicates that a circuit fault has occurred. This is true when the error indication remains after retransmission of the data word. If the error indication does not remain it ERROR INDICATION TO DISPLAY ...
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