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Unformatted text preview: DF TMR0 PC STATUS FSR PORTA PORTB EEDATA EEADR PCLATH INTCON EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 00H 01H 02H 03H 04H 05H 06H 08H 09H 0AH 0BH ;BANK0 ; DELAY_COUNT1 DELAY_COUNT2 COUNT EQU OPTIONR TRISA EQU TRISB EQU EECON1 EQU ; ; EQU EQU EQU EQU EQU EQU PROGRAM REGISTERS EQU 0CH EQU 0DH 0EH EQU 05H 06H 08H 01H ;STATUS BIT DEFINITION .0 .1 .2 .3 .4 .5 CF DC ZF PD TO RP0 ; Set output ports 0123456 to abcdefg of the 7-SEG ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;MAIN ROUTINE;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;INITIAL SETTING ORG BSF MOVLW MOVWF MOVLW MOVWF BCF 0 STATUS,RP0 B'11111111' TRISA B'00000000' TRISB STATUS,RP0 ;BANK1 ;A is input port ;B is output port ;BANK0 ;MAIN LOOP ;==========================Initial number MOVLW B'00111111' ;==========================Set to ‘0’ MOVWF PORTB BTFSC PORTA,2 ;Check switch. GOTO MAIN ;Pushed ’1’ WAIT until push CALL DELAY ;Not pushed ‘0’ GOTO SHOWTME MAIN ;=========================Display number when push the switch SHOWTME MOVLW B...
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This note was uploaded on 11/21/2010 for the course MECHANICAL mae302 taught by Professor Jang during the Spring '10 term at Seoul National.

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