# HW6 - 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 0

This preview shows pages 1–2. Sign up to view the full content.

Korea Advanced Institute of Science and Technology MAE307: Applied Electronics Professors Jung Kim, Jungwon Kim, and Inkyu Park ──────────────────────────────────────────────── Problem set 6 The solution should be submitted to the Room 2214, ME building (N7), before 1:00 PM at May 19. Grade deduction - Delayed submission: 50% of marked grade will be deducted - Cheating: Results ZERO grade for everyone involved Discussions on the problems are allowed. However, you MUST identify their names with student ID in your cover page of solution. ──────────────────────────────────────────────── Problem 1. Design the logic function defined by the following truth table and realize the function using only NAND gate. (don’t use AND or OR) A B C D F(output) 0 0 0

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 Problem 2. Draw a timing diagram (four complete clock cycles) for A0, A1, and A2 for the circuit of following figure. Assume that all initial values are 0. All flip-flops are negative edge triggered. Issue: May 11, 2010 Due : May 19, 2010 MAE307, Problem set 6 2 Problem 3. Draw the timing diagram with the assigned flip-flop types 1) Determine the output of the data-latch (R-S flip-flop) 2) Determine the output of the data-latch (R-S flip-flop) Problem 4. Construct the count sequence table of following counter, assuming the counter is initially cleared. Problem 5. Design the following sequence logic by using JK flip flops and draw the circuits. Don’t miss the following procedures. 1) State Transition Table 2) Excitation table for JK flip-flop 3) Karnough maps 4) Logic design...
View Full Document

## This note was uploaded on 11/21/2010 for the course MECHANICAL mae302 taught by Professor Jang during the Spring '10 term at Seoul National.

### Page1 / 2

HW6 - 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 0

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online