Computer-aided IC Design/VLSI I
(Prof. David Pan)
Homework #1 Solution
1.
a)
c
b)
x + yz
c)
ab + ac + ad + bc + bd + cd
2. Sketch the transistor-level schematic for a single-stage CMOS logic gate for the function, Y
= (AB + C.(A + B))'
3. Implement the logic function using three 2-to-1 multiplexers.
Problem is also intended to demonstrate the efficiency of designing with transistors (rather than
at the gate level).
The idea is to look at the function with respect to two of the variables, say a and b. For
example, when ab=00, when c=0, z=1, and when c=1, z=0, so we can say that z=c' (' is
complement here). We can similarly write the output for other combinations of ab from the set
{0,1,c,c'}.

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