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Computeraided IC Design/VLSI I
(Prof. David Pan)
Homework #4 Solution
1. Problem 4.19 from the Exercises for Chapter 4
NAND2: g=5/4; NOR2: g=7/4. The inverter has a 3:1 P/N ratio and 4 units of capacitance.
The NAND has a 3:2 ratio and 5 units of capacitance, while the NOR has a 6:1 ratio and 7
units of capacitance.
2. Problem 4.24 from the Exercises for Chapter 4
F = (10pF/20fF) = 500. N=log
4
F = 4.5. Use a chain of four inverters with a stage (note: 5
stages would work for the capacitance, but the polarity of the signal would be inverted).
D=4F
1/4
+ 4 = 22.9
τ
= 4.58 FO4 delays.
3. Problem 4.28 from the Exercises for Chapter 4
Dynamic power consumption will go down because it is quadratically dependent on V
DD.
Static power will go up because subthreshold leakage is exponentially dependent on V
t
.
4. Problem 6.10 from the Exercises for Chapter 6
NAND3: Hiskew, g
u
= 7/6, Loskew: g
d
= 4/3
NOR3: Hiskew, g
u
= 13/6, Loskew: g
d
= 4/3
5. Problem 6.12 from the Exercises for Chapter 6
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This note was uploaded on 11/21/2010 for the course EE 360R taught by Professor Pan during the Spring '10 term at University of Texas at Austin.
 Spring '10
 PAN

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