homework2_sol - (a) 0 (b) 0.6 (c) 0.8 (d) 0.8 7. Direct...

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Computer-aided IC Design/VLSI I (Prof. David Pan) Homework #2 Solution 1. (a) F = (((A + B) . C) + D)' (b) F = (X + Y).(X + Z) (c) F = a.b + a'.c + b.c.d
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(d) F = ((A + B + C).D.E)' 2. Problem 2.4 from the Exercises for Chapter 2. C permicron = ε L/t ox = 3.9*8.85*10 -14 F/cm * 90*10 -7 cm / 16 * 10 -4 μ m = 1.94 fF/ μ m 3. Problem 2.10 from the Exercises for Chapter 2.
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The current through an ON transistor tends to decrease because the mobility goes down. The current through an OFF transistor increases because V t decreases. A chip will operate faster at lower temperatures. 4. Problem 2.14 from the Exercises for Chapter 2. The main drawback of this circuit is that it can not pass full swing for both logic 1 and logic 0. 5. Problem 2.21 from the Exercises for Chapter 2. (a) 0 (b) 2|Vtp| (c) |Vtp| (d) VDD - Vtn 6. Problem 2.22 from the Exercises for Chapter 2.
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Unformatted text preview: (a) 0 (b) 0.6 (c) 0.8 (d) 0.8 7. Direct implementation is straightforward, but does not scale well, since the complexity increases quadratically. A design with repeatable cells, called an iterative logic array (ILA) makes for a tileable design. (You would have to insert buffers between a certain number of stages for performance.) In the ILA design, information needs to be passed between cells. For this problem, the obvious bit of information is whether a cell higher up had asserted priority, or not . If we encode this information for x, the intercell bit as x = 1 when no priority has been asserted, and x = 0 when an input higher up has asserted priority. We set the input value for x as 1. The resulting cell is: This can be mapped to CMOS transistors, but is just shown in logic form for clarity....
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homework2_sol - (a) 0 (b) 0.6 (c) 0.8 (d) 0.8 7. Direct...

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