This preview shows pages 1–4. Sign up to view the full content.
This preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
Unformatted text preview: (a) 0 (b) 0.6 (c) 0.8 (d) 0.8 7. Direct implementation is straightforward, but does not scale well, since the complexity increases quadratically. A design with repeatable cells, called an iterative logic array (ILA) makes for a tileable design. (You would have to insert buffers between a certain number of stages for performance.) In the ILA design, information needs to be passed between cells. For this problem, the obvious bit of information is whether a cell higher up had asserted priority, or not . If we encode this information for x, the intercell bit as x = 1 when no priority has been asserted, and x = 0 when an input higher up has asserted priority. We set the input value for x as 1. The resulting cell is: This can be mapped to CMOS transistors, but is just shown in logic form for clarity....
View Full
Document
 Spring '10
 PAN

Click to edit the document details