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Unformatted text preview: solution to any hold-time violation. Rise Fall CLK -> Q 500ps 500ps Flop Hold Time 750ps 750ps And Gate 300ps 200ps Inverter Gate 50ps 20ps 8. The flip-flop in the figure below has the delays of the various components labeled (delay of the NAND gate is G1, etc.) Find the approximate setup time , hold time and clock-to-QB delay in terms of the delays of the basic gates and inverters (example, delay = G1 + I2). Use the single value of delay (I3 and I4) for the dynamic and clocked inverters shown at the transistor level....
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- Spring '10
- Integrated Circuit, Logic gate, Inverter Gate, Prof. David Pan, Computer-aided IC Design/VLSI