homework6_sol - high rather than low Thus 11 2.5 = 13.5...

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Computer-aided IC Design/VLSI I Spring 2010 (Prof. David Pan) Homework #6 Solution 1. Problem 6.27 from the Exercises for Chapter 6. 2. Problem 6.31 from the Exercises for Chapter 6. The worst case is when A is low on one cycle, B, C, and D are high, and all the internal nodes become predischarged to 0. Then D falls low during precharge. Then A goes high during evaluation. The NAND has 11 units of capacitance on Cout precharged to VDD and 7.5 units of internal capacitance (C1, C2, C3) that will be initially low. The output will thus droop to 11/(11+7.5) VDD = 0.59 VDD.
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3. Problem 6.32 from the Exercises for Chapter 6. The droop is (6+5h)/(6+5h+7.5). Charge sharing is less serious at high fanout. 4. Problem 6.33 from the Exercises for Chapter 6. With a secondary precharge transistor, one of the internal nodes is guaranteed to be
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Unformatted text preview: high rather than low. Thus 11 + 2.5 = 13.5 units of capcitance are high and 5 units are low, reducing the charge sharing noise to 13.5/(13.5 + 5) VDD = 0.73 VDD. 5. Design the carry function for a full adder (C = AB + AC + BC) using standard Domino CMOS Logic , with the restriction that there are only three transistors (including clocking transistors) from any output node to ground. This is quite straightforward. The term, AB, AC and BC can be implemented with precharged NAND gates with an inverter (for the domino logic). The output function can be implemented with a precharged NOR gate with the inputs from the previous gates, and a final output inverter....
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This note was uploaded on 11/21/2010 for the course EE 360R taught by Professor Pan during the Spring '10 term at University of Texas.

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homework6_sol - high rather than low Thus 11 2.5 = 13.5...

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