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Unformatted text preview: high rather than low. Thus 11 + 2.5 = 13.5 units of capcitance are high and 5 units are low, reducing the charge sharing noise to 13.5/(13.5 + 5) VDD = 0.73 VDD. 5. Design the carry function for a full adder (C = AB + AC + BC) using standard Domino CMOS Logic , with the restriction that there are only three transistors (including clocking transistors) from any output node to ground. This is quite straightforward. The term, AB, AC and BC can be implemented with precharged NAND gates with an inverter (for the domino logic). The output function can be implemented with a precharged NOR gate with the inputs from the previous gates, and a final output inverter....
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This note was uploaded on 11/21/2010 for the course EE 360R taught by Professor Pan during the Spring '10 term at University of Texas.
 Spring '10
 PAN

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