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Unformatted text preview: 1 VLSI Design J. Abraham Spring 2006 EXAM. II April 12, 2006 Name: Exam, No. 1 Open Book, Open Notes. Time Limit: 75 minutes (pace yourself). Check for 5 pages in exam. Write all your answers in the spaces/boxes provided. Show any calculations in these pages using the back of the pages if needed. State clearly any assumptions made. 1. (20 points) The circuit below has the following parameters for the components: Clock period = 90 nS with a 50% duty cycle t clk- q = 40 nS t setup = 20 nS t hold = 45 nS AND gate delay = 15 nS OR gate delay = 20 nS Inverter delay = 5 nS Assume that the logic before F1 and after F2 has arbitrary slack and is impervious to timing issues. Q D Q D CLK F1 F2 (a) Will this circuit work correctly? Explain, and find the magnitude of the viola- tion, if any. (b) If you cannot move any cells, but can add inverters anywhere in the design, show the new design which fixes the violation but does not change the functionality....
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This note was uploaded on 11/21/2010 for the course EE 360R taught by Professor Pan during the Spring '10 term at University of Texas at Austin.
- Spring '10