Sample_exam1_solutio - Spring 2006 VLSI Design OUTLINE SOLUTIONS to EXAM I J Abraham March 1 2006 Name ECD STUDENT 1 1 a 9 5 c b 9 Size the

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J. Abraham Spring 2006 OUTLINE SOLUTIONS to EXAM I March 1, 2006 Name: ECD, STUDENT 1 1. Size the transistors in the circuit below so that it has the same drive strength, in the worst case, as an inverter that has PW = 3 and NW = 2. b a c d d b a c 9 9 9 5 4 2 4 4 2. Find the voltages at each of the nodes, A, B, C, D, E and F below. Use the following circuit parameters: V dd = 5 V , V tn = 0 . 5 V , | V tp | = 1 . 5 V . A B C F E D Vdd Vdd Vdd Vdd A = 5V B = 4.5V C = 4.5V D = 0V E = 1.5V F = 5V 3. Use the Elmore delay approximation to ±nd the worst-case fall delay at output F for the following circuit. The gate sizes of the transistors are shown in the ±gure. Use the assumption that the di²usion capacitance is equal to the gate capacitance and that a minimum sized transistor has gate and di²usion capacitance equal to C . The resistance of a nMOS transistor with unit width is R . Also assume NO sharing of di²usion regions. VDD
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This note was uploaded on 11/21/2010 for the course EE 360R taught by Professor Pan during the Spring '10 term at University of Texas at Austin.

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Sample_exam1_solutio - Spring 2006 VLSI Design OUTLINE SOLUTIONS to EXAM I J Abraham March 1 2006 Name ECD STUDENT 1 1 a 9 5 c b 9 Size the

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