sample_exam2_solution - (b) Critical delay = 200 + 200 +...

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Sample Exam II Solution (Fall 2006) 1. (8C + 5C) * 1.7V = (8C + 5C + 7C) * V’ V’ = 1.105V 2. setup time = 125 + 75 + 50 + 50 – 50 – 50 = 200 ps hold time = 0 ps clock-to-Q = 75 + 50 + 50 + 50 = 225 ps 3. (a) Critical delay = 200 + 200 + 200 + 300 = 900 ps Maximum clock frequency = 1111 MHz
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Unformatted text preview: (b) Critical delay = 200 + 200 + 300 = 700 ps Maximum clock frequency = 1428 MHz 4. (a) 4000 MHz (b) 100 ps (c) 100 ps (d) 100 ps 5. (a) path worst-case delay lowest delay BDFH 600 500 BEGH 425 300 BEFH 650 525 (b) (i) (101) (111) (ii) (010) (000) (iii) (000) (010)...
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This note was uploaded on 11/21/2010 for the course EE 360R taught by Professor Pan during the Spring '10 term at University of Texas at Austin.

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