{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

DSD chapter3 - ECSE 323 Digital System Design Combinational...

Info icon This preview shows pages 1–7. Sign up to view the full content.

View Full Document Right Arrow Icon
ECSE 323 Digital System Design Combinational Circuits Katarzyna Radecka [email protected]
Image of page 1

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Acknowledgements Material used in this set of slides was based on Fundamentals of Digital Logic with VHDL Design ” by S. Brown and Z. Vranesic
Image of page 2
Combinational Circuit Synthesis Classic two-level circuit synthesis Multilevel-circuit synthesis Factorization Decomposition Circuit synthesis using building blocks Sharing building blocks among output functions Multiplexers Decoders Look-up-table logic blocks General synthesis method
Image of page 3

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Classical Two-level Circuit Synthesis Design process starts from specifying the requirements and behaviour of a design Specification is then refined into behavioural circuit description given is VHDL, Verilog, or even C/C++ After checking its correctness w.r.t. specification the behavioural code undergoes a process of synthesis leading into a gate-level design The challenge of synthesis is to find the best netlist representation of the given design description Many classical approaches exist, which utilize the general common steps The first step is the conversion of behavioural description into a set of Boolean functions which logically relate inputs to outputs Then these functions are minimized to obtain a two-level circuit realization, using standard gates from a complete set, i.e. either {and,or,not}, {nand} or {nor} sets Note, that for CMOS implementations, the NAND/NOR realization is less costly than AND/OR
Image of page 4
Classical Two-level Circuit Synthesis, cont. In the previous lectures we discussed two-level logic optimization using K-Maps and Quine-McCluskey methods In general we can divide the logic optimization into two main categories: Two-level This form refers to the flattened view of a circuit in terms of SoP The final implementation is of the same form as the original function Literals are inputs which form implicants using multi-input AND gates The final circuit is obtained by using one OR gate to sum all the implicants Useful for PLA implementations Efficient for functions of a few variables (quite small) Multilevel More generic view of a circuit in terms of arbitrarily connected SoP (PoS) A node can be an arbitrary function We try to minimize a total number of nodes (blocks) in the circuit Example: Two-level vs. multilevel function representation Consider two functions: F1 = AB + AC + AD, F2 = A’B + A’C +A’E The above two-level representation requires six product terms and 24 transistors in CMOS implementation A possible functionally equivalent multilevel representation is: P = B + C, F1 = AP + AD, F2 = A’P + A’E Term P = B + C is shared by F1 and F2 reducing the number of product terms to two in F1 and F2
Image of page 5

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Example of Classic Two-level Circuit Synthesis EXAMPLE: DESIGN A FULL-ADDER CIRCUIT A full-adder is a device that adds in binary, three inputs, A, B, C in , and produces, two outputs: the sum, S, of the
Image of page 6
Image of page 7
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

What students are saying

  • Left Quote Icon

    As a current student on this bumpy collegiate pathway, I stumbled upon Course Hero, where I can find study resources for nearly all my courses, get online help from tutors 24/7, and even share my old projects, papers, and lecture notes with other students.

    Student Picture

    Kiran Temple University Fox School of Business ‘17, Course Hero Intern

  • Left Quote Icon

    I cannot even describe how much Course Hero helped me this summer. It’s truly become something I can always rely on and help me. In the end, I was not only able to survive summer classes, but I was able to thrive thanks to Course Hero.

    Student Picture

    Dana University of Pennsylvania ‘17, Course Hero Intern

  • Left Quote Icon

    The ability to access any university’s resources through Course Hero proved invaluable in my case. I was behind on Tulane coursework and actually used UCLA’s materials to help me move forward and get everything together on time.

    Student Picture

    Jill Tulane University ‘16, Course Hero Intern