# tut6 - Fig. 1, which shows the signal values with 1 ns...

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McGill University Department of Electrical and Computer Engineering Course: ECSE 323 -Digital Systems Design Fall 2010 ASSIGNMENT #6 Wednesday Oct. 13, 2010 TOPIC: Sequential Circuits Question 1 (problem 7.7 pp. 477) 35 points The gates SR latch in Figure 2 has unpredictable behavior if the S and R inputs are both equal to 1 when the Clk changes to 0. One way to solve this problems is to create a set- dominant gated SR latch, in which the condition S = R = 1 cases the latch to be set to 1. Design a set dominant gated SR latch. Figure 1: Circuit for Question 2 Solution

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Question 2 (problem 8.7 pp. 577) 35 points Derive the next-state expressions, that implement the state tables in Fig. 2. Figure 2: State Table for Question 2 Solution
Question 3 (problem 7.34 pp. 481) 30 points A circuit for a gated D latch is shown in Fig.1. Assume that the propagation delay through either a NAND gate or an inverter is 1 ns. Complete the timing diagram given in

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Unformatted text preview: Fig. 1, which shows the signal values with 1 ns resolution. Figure 3: Circuit and Timing Diagram for Question 3 Solution McGill University Department of Electrical and Computer Engineering Course: ECSE 323 -Digital Systems Design Fall 2010 ASSIGNMENT #6 Friday Oct. 15, 2010 TOPIC: Sequential Circuits Question 1 (problem 7.8 pp. 477) 35 points Show how a JK flip-flop can be constructed using a T flip-flop and other logic. Solution Question 2 (problem 8.1 pp. 578) 30 points An FSM is defined by the state-assigned table in Fig. 1. Derive the next-state equations that realizes this FSM using D flip-flops. Figure 4: State-assigned Table for Question 2 Solution Question 3 (problem 8.7 pp. 577) 35 points Derive the next-state equations, that implement the state tables in Fig. 1. Figure 5: State Table for Question 3 Solution...
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## This note was uploaded on 11/22/2010 for the course ECSE ECSE 322 taught by Professor Lowther during the Winter '04 term at McGill.

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tut6 - Fig. 1, which shows the signal values with 1 ns...

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