Lect 18 - 7 - EE 360M - Digital Systems Design Using VHDL...

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EE 360M - Digital Systems Design Using VHDL Lecture 18 Nur A. Touba University of Texas at Austin
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Arithmetic add subtract add immediate Logical and or and immediate or immediate shift left logical shift right logical Data Transfer load word store word Conditional branch branch on equal branch on not equal set on less than Unconditional branch jump jump register
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COMPONENTS OF DESIGN Components Instruction Fetch Unit Instruction Decode Unit Instruction Execution Unit Register File Memory
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INSTRUCTION FETCH UNIT Program Counter Special Register Pointing to Next Instruction PC_Branch = PC+4+Offset*4 PC_Jump = PC[31. .28] || Address*4 PC_JR = [REG]
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INSTRUCTION DECODE UNIT MIPS ISA Simple Decoding Opcode in First 6 Bits For R-Format Also Need to Look at Last 6 Bits Input Opcode to Controller Use Instruction Fields To Address Registers To Address Memory
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INSTRUCTION EXECUTION UNIT After Instruction Decoded Read Operands from Registers Register File Needs Two Read Ports Allow Reading Two Source Registers Register File Needs One Write Port Allow Writing to Destination Register Operands Sent to ALU ALU Contains Functional Units Adders, Shifters, etc.
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INSTRUCTION EXECUTION UNIT Required Data Path ALU Also Used for Non-Arithmetic Operations
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INSTRUCTION EXECUTION FLOW
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INSTRUCTION EXECUTION Can Implement Instruction Flow With Slow Clock Cycle Allow Each Instruction to Complete in One Cycle Disadvantage Cycle Long Enough for Slowest Instruction Fast Clock Cycle Each Instruction Takes Multiple Cycles Instructions Take Different Numbers of Cycles to Complete
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VHDL MODEL
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VHDL MODEL FOR REG FILE Register File Each Register 32-Bits Long Register Read Asynchronously When Synthesized for Xilinx Spartan FPGA Mapped as Distributed RAM
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entity REG is port (CLK: in std_logic; RegW: in std_logic; DR, SR1, SR2: in unsigned(4 downto 0); Reg_In: in unsigned(31 downto 0); ReadReg1, ReadReg2: out unsigned(31 downto 0)); end REG; architecture Behavioral of REG is type RAM is array (0 to 31) of unsigned(31 downto 0); signal Regs: RAM := ( others => ( others => '1')); -- set all reg bits to '1' begin process (clk) begin if CLK = '1' and CLK'event then if RegW = '1' then Regs(to_integer(DR)) <= Reg_In; end if ; end if ; end process ; ReadReg1 <= Regs(to_integer(SR1)); --asynchronous read ReadReg2 <= Regs(to_integer(SR2)); --asynchronous read end Behavioral;
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VHDL MODEL FOR MEMORY Address Big-Endian 30630000 Hex Little-Endian 30630000 Hex 1000 1001 1002 1003 30 63 00 00 00 00 63 30 MIPS Allows Byte Addressing For Simplicity Model is Word Addressable Order of Bytes Can Be Either Big or Little Endian Most Modern Microprocessors Support Both
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entity Memory is port (CS, WE, Clk: in std_logic; ADDR: in unsigned(31 downto 0); Mem_Bus: inout unsigned(31 downto 0)); end Memory; architecture Internal of Memory
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This note was uploaded on 11/30/2010 for the course EE 316 taught by Professor Brown during the Fall '08 term at University of Texas at Austin.

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Lect 18 - 7 - EE 360M - Digital Systems Design Using VHDL...

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