Lect7 - 6 - EE 316 - Digital Logic Design Lecture 7 Nur A....

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EE 316 - Digital Logic Design Lecture 7 Nur A. Touba University of Texas at Austin
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UNIT 7 Unit 7 Multi-Level Gate Circuits Number of Levels of Gates Maximum number of gates between input and output Normally assume inputs driven by flip-flops All variables and their complements are available Don’t count inverters
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TERMINOLOGY AND-OR Circuit Two-level, level of ANDs followed by level of ORs Directly implement Sum-of-Products OR-AND Circuit Two-level, level of ORs followed by level of ANDs Directly implement Product-of-Sums OR-AND-OR Circuit Three-level, OR level, AND level, OR level Circuit of AND and OR No ordering of ANDs and ORs
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ISSUES In AND-OR, Number of Levels Usually Increased by factoring SOP In OR-AND, Number of Levels Usually Increased by multiplying out some terms in POS Issues More level may reduce total number of gates and gate inputs - reduce cost Number of gates that can be cascaded limited by gate delays Slows down propagation delay
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FINDING LEVELS FROM EXPRESSION
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FINDING LEVELS FROM EXPRESSION Change to 3 Levels by Partially Multiplying Out
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EXAMPLE Find Two-Level and Three-Level circuits to implement f(a,b,c,d) = Σ m(1,5,6,10,13,14)
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This note was uploaded on 11/30/2010 for the course EE 316 taught by Professor Brown during the Fall '08 term at University of Texas at Austin.

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Lect7 - 6 - EE 316 - Digital Logic Design Lecture 7 Nur A....

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