# Lect8 - 3 - EE 316 - Digital Logic Design Lecture 8 Nur A....

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EE 316 - Digital Logic Design Lecture 8 Nur A. Touba University of Texas at Austin

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UNIT 8 Unit 8 Combinational Circuit Design and Simulation Combinational Design Generally Start from Truth Table Derive Simplified Expression with K-Maps Alternatively Start from Algebraic Expressions Simplify Algebraically May Factor to Reduce Gates or Gate Inputs Increases Number of Levels For Multi-Output, Minimum May Not Use Only Prime Implicants for Individual Outputs
DESIGN WITH LIMITED FAN-IN Maximum Number of Inputs to Gate May be Limited If Two-Level Uses More Gate Inputs Than Allowed Need to Factor to Obtain Multi-Level Circuit

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EXAMPLE
MULTI-LEVEL MULTI-OUTPUT Techniques for Two-Level Multi-Output Design Not Effective for Multi-Level Usually Better to Individually Minimize Factor to Introduce Common Terms

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EXAMPLE
EXAMPLE

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PROPAGATION DELAY Propagation Delay Delay from Input Change Until Output Changes May Have Different Delays for Output Rising from 0 to 1 Output Falling from 1 to 0
TIMING DIAGRAM Timing Diagram Shows How Signals Change as Function of Time Several Signals Plotted with Same Time Scale Shows how change w.r.t. each other

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## Lect8 - 3 - EE 316 - Digital Logic Design Lecture 8 Nur A....

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