Lect8 - 3 - EE 316 - Digital Logic Design Lecture 8 Nur A....

Info iconThis preview shows pages 1–10. Sign up to view the full content.

View Full Document Right Arrow Icon
EE 316 - Digital Logic Design Lecture 8 Nur A. Touba University of Texas at Austin
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
UNIT 8 Unit 8 Combinational Circuit Design and Simulation Combinational Design Generally Start from Truth Table Derive Simplified Expression with K-Maps Alternatively Start from Algebraic Expressions Simplify Algebraically May Factor to Reduce Gates or Gate Inputs Increases Number of Levels For Multi-Output, Minimum May Not Use Only Prime Implicants for Individual Outputs
Background image of page 2
DESIGN WITH LIMITED FAN-IN Maximum Number of Inputs to Gate May be Limited If Two-Level Uses More Gate Inputs Than Allowed Need to Factor to Obtain Multi-Level Circuit
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
EXAMPLE
Background image of page 4
MULTI-LEVEL MULTI-OUTPUT Techniques for Two-Level Multi-Output Design Not Effective for Multi-Level Usually Better to Individually Minimize Factor to Introduce Common Terms
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
EXAMPLE
Background image of page 6
EXAMPLE
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
PROPAGATION DELAY Propagation Delay Delay from Input Change Until Output Changes May Have Different Delays for Output Rising from 0 to 1 Output Falling from 1 to 0
Background image of page 8
TIMING DIAGRAM Timing Diagram Shows How Signals Change as Function of Time Several Signals Plotted with Same Time Scale Shows how change w.r.t. each other
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 10
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 31

Lect8 - 3 - EE 316 - Digital Logic Design Lecture 8 Nur A....

This preview shows document pages 1 - 10. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online