Lect9 - 4 - EE 316 Digital Logic Design Lecture 9 Nur A...

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EE 316 - Digital Logic Design Lecture 9 Nur A. Touba University of Texas at Austin
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UNIT 9 Unit 9 Multiplexers, Decoders, and Programmable Logic Devices Integrated Circuits SSI ~10 Gates (NAND, NOR, Flop-Flops, etc.) MSI ~100 Gates (Adders, Registers, Counters, etc.) LSI ~1000s Gates (Memories, Microprocessors, etc.) VLSI >> 10,000
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MULTIPLEXERS 2-to-1 MUX 4-to-1 MUX General MUX
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MULTIPLEXERS Used When Constructing Bus Avoids Point-to-Point Connections
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MULTIPLEXERS Inverting Multiplexers Will be Referred to as MUX with Active Low Output Non-Inverting is MUX with Active High Output Enable Signal Active High Enable Enable = 1 for MUX Operation Active Low Enable Enable = 0 for MUX Operation
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BUFFER Buffer Used to Increase Driving Capability Allows More Fanout from Output of Gate Non-Inverting
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TRI-STATE BUFFER Tri-State Buffer Buffer with Enable Signal When Not Enabled, Does Not Drive Output Leaves in High-Impedance (Hi-Z) State Output can be 0, 1, or Z
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This note was uploaded on 11/30/2010 for the course EE 316 taught by Professor Brown during the Fall '08 term at University of Texas.

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Lect9 - 4 - EE 316 Digital Logic Design Lecture 9 Nur A...

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