Lect10 - 4 - EE 316 - Digital Logic Design Lecture 10 Nur...

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EE 316 - Digital Logic Design Lecture 10 Nur A. Touba University of Texas at Austin
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UNIT 10 Unit 10 Introduction to VHDL Hardware Description Language Textual way to describe hardware Can be used as input to synthesis tool Tool compiles and produces netlist Analogous to writing software in high-level language and compiling to machine langauge
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HARDWARE DESCRIPTION LANGUAGE Two Most Popular HDLs VHDL Verilog VHDL - VHSIC Hardware Description Language VHSIC - Very High Speed Integrated Circuit Originally developed for specifying hardware Became IEEE Standard in 1987 Revised in 1993
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VHDL Can Describe Digital System at Different Levels Behavioral - Adder adds two binary numbers Data Flow - Boolean Equations for Adder Structural - Netlist for Adder Allows Top-Down Design Describe at High-Level Simulate, Debug Refine to Lower-Level End up at Structural Level
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DESCRIBING GATES IN VHDL Behavior Description of Gates Dataflow Description of Gates A B C D E C <= A and B after 5 ns; E <= C or D after 5 ns; E <= D or (A and B)
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DESCRIBING GATES IN VHDL Structural Description of Gates A B C D E Gate1: AND2 port map (A, B, C); Gate2: OR2 port map (C, D, E);
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DELTA DELAYS If No Propagation Delays Specified Delay is 0 ns Simulator uses Infinitesimal Delay (Delta) C <= A and B; E <= C or D;
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CONCURRENT STATEMENTS Order of Concurrent Statements Unimportant C <= A and B; E <= C or D; E <= C or D; C <= A and B;
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SIGNAL ASSIGNMENT General Form of Signal Assignment signal_name <= expression [ after delay]
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INVERTER WITH FEEDBACK CLK <= not CLK after 10 ns;
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Lect10 - 4 - EE 316 - Digital Logic Design Lecture 10 Nur...

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