Lect12 - 2 - Does Not Work with Single Throw Switch...

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EE 316 - Digital Logic Design Lecture 12 Nur A. Touba University of Texas at Austin
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UNIT 11 Latches and Flip-Flops Sequential circuits depend on present and past inputs Need memory Memory devices with two states Flip-Flop Responds to changes in clock input Latch No clock input Responds to changes in data input
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FEEDBACK Feedback Needed for sequential circuits
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FEEDBACK Two Stable States
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SET-RESET LATCH
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SET-RESET LATCH Cross-Coupled Form
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TIMING DIAGRAM FOR S-R LATCH Input Pulse on S (or R) Needs to be at least ε for gate output to change and latch to change state
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S-R LATCH Present State Q(t) or Q Q output when input signal changes Next State Q(t+ ε ) or Q + Q output after reacting to input change Q+ = R’S + R’Q P = S’Q’ (Same as Q’ except when S=R=1)
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S-R LATCH
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DEBOUNCING WITH S-R LATCH Assumes a Double Throw Switch Does Not Work with Single Throw Switch
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Unformatted text preview: Does Not Work with Single Throw Switch S’-R’ LATCH GATED D LATCH GATED D LATCH ☞ Characteristic Equation EDGE-TRIGGERED D FLIP-FLOP TIMING FOR D FLIP-FLOP ☞ Falling-Edge Triggered D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP S-R FLIP-FLOP Operation summary: S = R = 0 no state change S = 1, R = 0 set Q to 1 (after active Ck edge) S = 0, R = 1 reset Q to 0 (after active Ck edge) S = R = 1 not allowed S-R FLIP-FLOP J-K FLIP-FLOP J-K FLIP-FLOP J-K FLIP-FLOP T FLIP-FLOP Q+ = T'Q + TQ' = Q ⊕ T T FLIP-FLOP D-FF WITH CLEAR AND PRESET D-FF WITH CLEAR AND PRESET ☞ Asynchronous Clear and Preset GATING CLOCK FLIP-FLOP VERSUS LATCH ☞ Characteristic Equation • For Latch • Q+ is state of latch short time after input change • For Flip-Flop • Q+ is state of flip-flop short time after active clock edge...
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