# Lect14 - 3 - EE 316 - Digital Logic Design Lecture 14 Nur...

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EE 316 - Digital Logic Design Lecture 14 Nur A. Touba University of Texas at Austin

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UNIT 13 Analysis of Clocked Sequential Circuits Construct State Graph/Table Study Timing Relationships
SEQUENTIAL PARITY CHECKER Parity for Error Detection Extra Bit Added to Make Number of 1’s in Word Always Odd (Odd Parity)

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SEQUENTIAL PARITY CHECKER Check if Number of 1’s Received is Odd
SEQUENTIAL PARITY CHECKER

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ANALYSIS BY SIGNAL TRACING Assume an Initial State of FFs All FFs Reset to 0 unless otherwise specified For First Input in Sequence Determine Circuit Output(s) and FF Inputs Determine New Set of FF States after Clock Edge Determine Output(s) Corresponding to New States Repeat for Each Input in Given Sequence
TWO TYPES OF CIRCUITS Moore Machine Output Associated with State Mealy Machine Output Associated with Input and State Arrow Between States

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MOORE EXAMPLE Input Sequence: X = 01101 Initial State: A=B=0
MOORE EXAMPLE Timing Diagram

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MEALY EXAMPLE Input Sequence: X = 10101 Initial State: A=B=0
MEALY EXAMPLE Timing Diagram

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## This note was uploaded on 11/30/2010 for the course EE 316 taught by Professor Brown during the Fall '08 term at University of Texas at Austin.

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Lect14 - 3 - EE 316 - Digital Logic Design Lecture 14 Nur...

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