Lect16 3 - EE 316 Digital Logic Design Lecture 16 Nur A Touba University of Texas at Austin UNIT 15 Reduction of State Tables Before realizing

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EE 316 - Digital Logic Design Lecture 16 Nur A. Touba University of Texas at Austin
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UNIT 15 Reduction of State Tables Before realizing state table Reduce to minimum number of states State Assignment Assign binary flip-flop codes to each state Affects amount of logic required Finding best state assignment difficult Can use general guidelines
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EXAMPLE 1 Design Mealy Circuit Examine groups of four consecutive inputs Z=1 if 0101 or 1001 occurs Reset after each group of four X = 0101 | 0010 | 1001 | 0100 Z = 0001 | 0000 | 0001 | 0000
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STATE TABLE
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REDUCED STATE TABLE
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EQUIVALENT STATES Two States, s i and s j Equivalent IFF Give Exact Same Output Sequence For Any Possible Input Sequence X Theorem 2200 λ ( p,X ) = λ ( q,X ) and δ ( p,X ) δ ( q,X )
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IMPLICATION TABLE
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STATE TABLE REDUCTION Final Reduced State Table
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IMPLICATION TABLE Steps Construct chart with square for every pair of states If outputs for states i and j differ Place X in square If outputs same, but next state differ Placed implied next state pair
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This note was uploaded on 11/30/2010 for the course EE 316 taught by Professor Brown during the Fall '08 term at University of Texas at Austin.

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Lect16 3 - EE 316 Digital Logic Design Lecture 16 Nur A Touba University of Texas at Austin UNIT 15 Reduction of State Tables Before realizing

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