Syllabus - Syllabus for EE 316 Digital Logic Design Course EE316 Digital Logic Design Term Fall 2010 Lecture TuTh 2-3:30pm in ENS 127 Unique No

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Course: EE316 – Digital Logic Design Term: Fall 2010 Lecture: TuTh 2-3:30pm in ENS 127 Unique No.: 16210 Instructor: Prof. Nur A. Touba Office: ACES 6.132 Phone: 232-1456 Email: [email protected] Office Hours: TuTh 1-2pm in ACES 6.132 or by appointment Teaching Assistants: Name Email Lab Sections Faisal Iqbal [email protected] W 11-12pm, W 2-3pm YoungTaek Kim [email protected] Tu 12:30-1:30pm, Th 11-12pm Mukund Kalyanaraman [email protected] M 3-4pm Suriya Gunasekar [email protected] M 1-2pm Karthik Shankar [email protected] M 10-11am Lab: ENS 202 (316 Lab) Lab Hours: Mon. 10am-5pm Tue. 10am-5pm Wed. 10am-5pm Thur. 10am-5pm Fri. 11am-5pm Description: This course teaches the principles of digital logic design and includes a lab component. The topics covered include the following: Boolean Algebra Karnaugh Maps Analysis and Design of Combinational Logic Latches, Flip-Flops, Registers, Counters Multiplexers, Decoders, and Programmable Logic Devices Analysis and Design of Sequential Circuits Introduction to VHDL Applications to Computer Design Prerequisite: EE 306 or CS 307; and credit or registration for EE 312 or CS 310. Required Textbook: Fundamentals of Logic Design , by C.H. Roth and L.L. Kinney, Cengage Learning, Sixth Edition, ISBN 0-495-47169-0. Earlier editions cannot be used as they do not contain all the new material and exercises.
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This note was uploaded on 11/30/2010 for the course EE 316 taught by Professor Brown during the Fall '08 term at University of Texas at Austin.

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Syllabus - Syllabus for EE 316 Digital Logic Design Course EE316 Digital Logic Design Term Fall 2010 Lecture TuTh 2-3:30pm in ENS 127 Unique No

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