Lecture 6-7 - Lectures 6-7 – – • Announcements – Hwk 2 due Friday beginning of discussion section – Hwk 3 posted – Make sure to check

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Unformatted text preview: Lectures 6-7 – 9/8/10 – 9/10/10 • Announcements – Hwk 2 due Friday beginning of discussion section – Hwk 3 posted – Make sure to check Blackboard for corrections to assignments • Last Week – Combinational logic circuits • This Week (P&P 3.4-3.6) – Storage – Sequential logic – Clocks • Next Week – Finite State Machines – Let’s Build a Computer CS310 Fall 2010 - Boral Storage • Ideally: inexpensive, large & fast - Can’t have all three • Computer programs exhibit locality of reference – Reasonable likelihood that: • A memory address will be referenced again soon (instruction in a loop) • A nearby memory address will be referenced soon (array processing) CS310 Fall 2010 - Boral R-S Latch • Two interconnected NAND gates • Quiescent when R == S == 1 – If a == 1: A = 1, b = 0, B =0 • a won’t change as long as R & S remain == 1 • The R-S latch stores the value “1” – If b == 1: B = 1, a = 0, A = 0 • b won’t change as long as R & S remain == 1 • The R-S latch stores the value “0” • We have two stable states – Can thus store a bit! • We say that the latch stores a “1” when a == 1 – b, the 2 nd output, is the inverse of the stored value CS310 Fall 2010 - Boral Changing the Latch’s Value • To set the latch to “1” – Set S = 0 for a “moment” – Keeping R == 1 – A gets set to 1 – Reset S = 1 after the “moment” • To set the latch to “0” – Set R = 0 for a “moment” – Keeping S == 1 – B gets set to 1 – Reset R = 1 after the “moment” • Avoid setting R = S = 0...
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This note was uploaded on 11/30/2010 for the course CS 310 taught by Professor Fussell during the Spring '08 term at University of Texas at Austin.

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Lecture 6-7 - Lectures 6-7 – – • Announcements – Hwk 2 due Friday beginning of discussion section – Hwk 3 posted – Make sure to check

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