schedule - Tentative Schedule for EE 316 Digital Logic...

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Tentative Schedule for EE 316 – Digital Logic Design Thu., Aug. 26 - Introduction and Number Systems and Conversion (Unit 1) Tue., Aug. 31 - Boolean Algebra (Unit 2) Thu., Sep. 2 - Boolean Algebra (Unit 3) Tue., Sep. 7 - Applications of Boolean Algebra (Unit 4) - Homework #1 Due (Unit 1, 2 problems) Thu., Sep. 9 - Karnaugh Maps (Unit 5) Tue., Sep. 14 - Karnaugh Maps (Unit 5) - Homework #2 Due (Unit 3, 4 problems) Thu., Sep. 16 - Multi-Level Gate Circuits NAND and NOR Gates (Unit 7) - Lab #1 Due (Unit 4 Lab) Tue., Sep. 21 - Combinational Circuit Design (Unit 8) Thu., Sep. 23 - Multiplexers, Decoders, and Programmable Logic Devices (Unit 9) - Homework #3 Due (Unit 5, 7 problems) Tue., Sep. 28 - Multiplexers, Decoders, and Programmable Logic Devices (Unit 9) Thu., Sep. 30 - Review for Quiz 1 - Homework #4 Due (Unit 8, 9 problems) Tue., Oct. 5 - QUIZ 1 Thu., Oct. 7 - Introduction to VHDL (Unit 10) Tue., Oct. 12 - Introduction to VHDL (Unit 10) - Lab #2 Due (Unit 8 Lab) Thu., Oct. 14 - Latches and Flip-Flops (Unit 11)
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