ex2_sol_f09 - EEL 4744C — Dr. Gugel Last Name Kg V! First...

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Unformatted text preview: EEL 4744C — Dr. Gugel Last Name Kg V! First Name Fall 2009 Exam #2 UF|D# - Open book and open notes, 90-minute examination to be done in pencil. o No electronic devices are permitted. ° All work and solutions are to be written on the exam where appropriate. Point System (for instructor and TA use only) Page 2 26 points DA”; "V‘ Page 3 22 points M "M Page 4 8 points Ali/L57?“ Page 5 24 points AAng Page 6 10 points fifl/W‘M Page 7 14 points fl/m’“ TOTAL out of 100 GraEEReview information: (NOTE: deadline of request for grade review is the day the exam is returned.) 1. A student would like to add a 16 bit output port and a 16 bit input port to their lab DSP board. However they don’t want to add any extra components other than those already on our DSP board. Use only the devices we provide on our board! Show how this can be accomplished with our DSP board and label all "0 signals as well as the circuitry required for address decoding. Assume that the output and input ports will be mapped to the same address and that there will be 256 images of this hardware in the memory map. Use DSP signals that will yield the least amount of address decoding circuitry required in the CPLD. i.e. Select DSP signals that will optimize your CPLD design. DO NOT use GPIO pins on the DSP to create the ports. Hint: The CPLD on your board can do more than just address decoding. Note: The simplestdesign will receive the highest pts. (18 pt.) / £30 3;? [foo-0.. O‘Oolxxyylxm/ l DSPGMip‘A: port 9%er W000 « ibFF) r , ovfl’i W {to . 4 -wm‘ ; A“ '% ,WlZF . ’CSO Do M NO 12/55 /0 will? 0 j:pr Peri. ’RDT ,gm 95? /C60 INIE /‘9 big it ’8/‘5 «of D0 0 . p Dlgto M) t CPLD iri’slfi‘fi/D ‘ DS ' 1 CM) orbits. 0w , Dsr Artsy/€302 ’4‘” CPLD INM; : IN 15-0 2 (a me?“ 2. What is the address range for your ports (all 256 images) in your above design? (2 pt.) ’ p‘ Ck’ngNa we, VFW; 3. Briefly write the steps required to initialize the DSP signals needed in your above design. i.e. pseudo code You may assume register names and are available for use. i.e. GPE_IOMux1 = OXFFOO ;select GPEIO outputs 15:8 (6 pt.) p0 MUD” : 0X FFFFFFFF 7 $24M?" XD/glo For in comma/Tim was ‘ at rcso a: ray carter WF “WWW/W 'Se/cd‘ 61/2me C , /N Peace/£3 2 €57“ X‘T/McH/J/ W .3 P 2 are max 2 i, @fgsgafaj‘SS/Walfw/wg l)! /X My r : ~ ‘ ' Ali AIM? I98 4. Write code to read the input port and continuously echo it out the output port. (4 pt.) 46?: may AROWOHW Mov flLZ at/yl/EO MW Wheon AL )3 763) (we 5. After successfully adding the 16 bit external l/O port to their board, the student has found a large high speed SRAM that is 256Kx8 in size Assuming that the device is fast enough to connect to our DSP, show all the required connections and SRAM diagram below to create a 512Kx16 block of external memory. Also show the required address decoding that will be placed inside the DSP board’s CPLDA As in the previous problem, select DSP signals that will minimize the circuitry required in the CPLD‘ Assume full address decoding for the SRAM block and assume the SRAMs have similar specifications as the ones you used in your lab. (16 pt.) k :17; 28. Z”): Z ,8 fil?:& 5/2/< a? 2ft - 2’”: g"? A 13353 D9? “6 W} as? ‘ l‘é W‘Wfl g :33? my? mm» g8 ‘ fill?” film _ D736. us was mm W i W «’RD’W/Euflw" ’20 firmer; i a «£54? wee l s m ) I: « g M 6 Air/433’; i Hg i {Oxloooom-OxIFFFFF C' ’0‘ Wu) 4% WEE/A - 4,3 .goooo wirrrrr (000w * I7FFFF ow Page Score = 6. Specify the address range for your SRAM block in Hex. (2 pt.) Page 3 KW: {wager’ 2w 7. Assuming that the required DSP signals have been already initialized in software, write the necessary to place 0xAA55 in the highest1Kwordsof SRAM. (8 pt.) H; k“? (K : {jgcoowl‘iFFFF $7an .SE‘T oxl7Fcao 3 W W Cflun’i’ 515T 025‘ (jaw; fligy 36 0);}, % 2401).; ,Mfiomt/ ,’ Aug Lazy MOD/é, X I20) 5779M ______._______..___ ADD M, «rm/W; emf-amt; _W____ W WW B- ) aorta" Upon running several memory tests on the SRAM, the student notices some intermittent errors. Therefore the student decides to review the DSP timing diagram and the SRAM timing specifications as follows: DSP Read / Write Cycle Timing Diagram 93p R/~W , .. I - ' ' g : Tzfl 9143 T5 T1 ‘W I ‘ V H . , . :33? A1920 ‘ > ' :33? as); {ESP-«RD {only present: on Read cycle) [315:0 (read) . g 915:9 (write) i «SRAMMCE : " ‘ ' 37 l T1 2 Read/Write True to Valid Addr, 40 use: 5 Read Data Setup m m nsec T2 = Valid Addr to ~68}: True, 40 neec Read Data field = 3 nsec T3 = 425): 'f‘r‘ue to ~42!) True, 25 nsec T4 3 —RD True Width, 36 nsec Write Data Setup 2 17 TS x ~RD False to «68;: False, 23 use: Write Data Hold :: 5 Write SRAM Specifications (min/max nsec): Read SRAM Specifications (min/max nsec): R/-W Low to Valid Addr = 3/* R/-W High to Valid Address = 3/* I Valid Addr to —CE True = 15/* Valid Addr to —CE True = 15/* —CE Width = 15/* -CE Width = 15/* Data Setup time = 12/* -CE True to ——OE True = 3/* Hold time = 3/* —0E False to —CE False = 3/* Hold time After —OE or —CE False = 3/7 * indicates no maximum requirement Memory Access Time (—OE AND —-CE True) = 19/22 Page 4 Page Score = 8. On the DSP Timing Diagram on the previous page, draw in the setup and hold times for the DSP Read and Write cycles. indicate the times with an R or W at the end of the time values drawn to show which are for Read and which are for Write. (4 pt.) 6/ fl rm. 9. Show with arrows on the previous timing diagram ere data is latched by the SRAM and the DSP. (2 pt.) See. MW 10. Draw the —SRAM_CE in the previous timing diagra assuming a CPLD with zero propagation delay. (3 pt) seam 11. What is the CPLD propagation delay (tcpld) rae t 1 _ MW}? e‘ - if 596ng 73 “(SE (A D5? «a $12M ’ 4mg? 5 W amcwycégyg . L 513% , I” '5 {45’ 5 ,7 [Z we” héw‘imy‘ Mi nemesis than: manger: Safe if flag!) 6} fl 21:5; M 3 0k: 5‘0 slide mini 52- ééfwe Ky“: 26 am» 72/» 7’5 42, 2 26+ 30 wee/2,4 Q55 12. What is the CPLD propagation delay (topm) range that will meet the DSP & SRAM READ timing specifications. (5 pt.) ,‘F 149,944) :0 ) «mime :1’ grille e625” Z§ xi, .5er we!) DSP Safwa lite/J’s? 30’22’3 5/136 “CE 26;} Sell??? 247,225? WW5?!” my» ficecfifi 22. b 3’ I 2;» 5 1.033 337 3: 14. Will a 10 nsec CPLD (like the one you ha '4 ""- rymeer‘bb‘flr'the Write & Read y-flS 15. If the SRAM has an additional requirement that the —-OE width be at least 40 nsec, what can be done to meet this specification (along with the others previously mentioned for the Read cycle)? Your answer should be very detailed (and correct) to receive the highest number of points. (3 pt.) _ H I l y' - [fig it fi’fl‘i’) ing specifications? (2 pt.) Page 5 Page Score = After the student has successfully implemented the 16 bit l/O port (problem #1) and the SRAM (problems #4—#12), they now would like to add a high speed LCD to their DSP board. The device that is available has the following signals and timing diagram. High Speed General Purpose LCD Show the connections required 9 belaw. Label all signals! Power/6ND Not Shown For Brevity Purposes R/-W as _, ' g - é 087:4» ' 3 g * indicates no maximum requirement 16. Assuming that the LCD will be interfaced to a DSP with timing specifications shown on page 4, show the connections on the LCD such that the LCD is interfaced in a manner to take full advantage the bus cycle speed on the LCD and minimize the time it takes to send characters to the LCD. is Optimize the DSP processing time by interfacing the LCD in the fastest manner possible. You may use any DSP signals that are available. The best design will receive the highest points. You may also use the space below for additional required circuitry. (10 pt.) I v.6 3,“ 621575; ‘ [236$ l Page 6 Page Score = 17. Once the LCD has been interfaced to the DSP board, we would like to now use it to send out ASCII characters received in through the buffer added in problem #1. i.e. A device has been connected to the input buffer such that one (8) bit character is output to the 16 bit input buffer on the upper byte of the buffer. Assuming the LCD has already been initialized, create a SUBROUTINE to read the upper byte of the buffer and send it out to the LCD one time. You do not need to preserve the registers corrupted by this routine. (4 pt.) acho_cnar WWW P012 4% 0xé/0w ‘69un do" [ML/9’3 '0 76M“; Wm MRI may A‘Xflfl/ HA W ___.__.__.___7Lfl——i 4&0) + I ‘ LCD a/aé. WV ,4 W6 ' 54” La [MW t fifimfl cm LSIQ ' 9 ' 'a/I‘VL wcw w e 18. The device that outputs one character at a time to our attached buffer does so at an update rate of 75 Hz. i.e. One new ASCII character every 1/75 seconds on the upper byte of the buffer inputs. Using polling, write code to call your subroutine in #17 every 1/ 150 seconds which is twice the rate of the device connected to the buffer. Initialize all the required registers for this design as well as the code that is required to poll and call your routine above. (10 pt.) W WW men/nee taxczgo W'WEKGPI) .557 0X6w>>é WV firms/(Wm $0 @350 : 502000 MW meg/PK o 75MH%1-/56H2:: 501000 WOV ImE/e I42 4&0 57’ //’W€I< C 4&5 flax femth z/zcsoafiew j cluk 7795M? (TIP) AC Eclw— Ck” m5 2 dew 77? I MAIL—.— meal? framfl‘i 1%2 CW __________+____________ AND a; itax mo W W Page 7 Page Score = w/ ...
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ex2_sol_f09 - EEL 4744C — Dr. Gugel Last Name Kg V! First...

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