fq_sol_s10 - EEL 4744C — Dr Gugel Print Your Last Name[Z...

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Unformatted text preview: EEL 4744C — Dr. Gugel Print Your Last Name [Z 2 Spring Semester 2010 \ Final Quiz Print Your First Name Hal/x0 5 0 Open book/open notes, 90 minute examination. Calculators are permitted. No laptops or cell phones. iPADs allowed. Page 1 17 points 2 Al’s/75W” Page 2 17 points Min/why» Pages 3 & 4 16 points AMYLMA TOTAL 50 points % A/D & D/A Conversion You are given a microphone that has a maximum output span of 100mV. it is attached to a pre—amplifier that has split supply rails of +I- 9V (using standard 9V batteries) and a gain of 50. Assuming that a 14 unsigned AID will be used to digitize the signal coming from the preamplifier answer the following questions. i 1. Assuming that the A/D converter is also powered from the two 9V batteries, what should the reference voltages be set i to on the A/D converter assuming that the device is DC coupled? i.e. There is no large capacitor blocking DC between 3 the preamplifier output and A/D converter? Assume we desire maximum accuracy when digitizing the analog signal. (2 pt.) l/flH: {2.5V (0on X50=5V izsv ~ ' VflL:/Z‘5V 2. if the A/D voltage references have been set to +I- 6V (to have 3V headroom with respect to the power supply rails), what is the resolution and accuracy of the A/D system? (4 pt.) i i l i c f. A *lo 70 l2 6 0‘73'2/MV Ac lamp? Sigma} Spam 0 Air/ark, : 005% 112; 24 fir 5 3. lfthe A/D references have been set to +/— 6V, what digital value is expected (in decimal) for a +2.57V analog input? “'0‘” errr +65 M c a I A’ (W 21:7— l " “’ irrr ov 13. mm as atom i i i l l l l a . i a i l l l x o , G i ll 7 02, l 4. If the A/D references have been observed to have ‘ e on them, what is the dynamic range of the A/D and what is the new expected digital output range for a +2. 7V analog input? (4 pts.)i~ 005' 1 ’M; vgo- /$6‘g3¢< / ZV i 7’ 7,0 /0 ( 'Ofi) ” i 5 It 5. If the A/D references are again +/— 6V and the span of the input analog signal 0 er has been observed to be +/- 7V. how will the frequency content of the input signal be altered by the clipping? Be very specific in your answer for maximum points. Also, if there is no low pass filter on the input to the A/D how can this cause additional problems? (4 t.) . l p cm? M454; Ell/ii?) cliff“ ‘ 1”"; “Lani” 0AM l g l x ; , 6. You are given a Signed 14 bit BIA with a reference span set to 3.3V, what is the expected output for 0x3EEE? (3 pts.) - H No mo mo 34‘ , "i 0 MW H mo lllo Help 259 Z ’ 3682 a? 03 cool cool carol/72.1: ’Z7y)6/_\+[,(pg a. W I 1000 0V ’ “2/74— 0 0552M 7. Using the above D/A converter, what four values (samples) should be sent to the BIA to create a triangle wav ’ ; spans the entire 3.3V output range? The best waveform (answer) stored in memory will receive the most points! (4 pt.) l F9? 0 /\O CO!) 2 . [Val1 (Hex) = 2000 Va|2 (Hex) = O Val3 (Hex) = “’77; Val4 (Hex) = O 8. We would like to use a potentiometer connected to an 8 bit unsigned AID converter to control the period of the triangle wave created in #7 above. Specifically, we would like to output the memory values in #7 above such that a waveform is generated that has a frequency from 100-1 OK Hz. Assuming that we have a processor with a 16 bit timer running at 10 Mhz (you may assume the pre-scaler has been set to one), what timer values should correspond to 0V and full scale on the AID? Assume the timer works similar to the one we have on our DSP, where it counts down to zero and sets a flag/interrupt. (4 Pt) F g, 6100 , [7/0 [C W 5 ’ ' C7 (Oxb , Zamog‘l‘wm /’9 $400 ?. Io/xloi’ :. 250 WW 4/6000 9. To create a smooth change in output frequency based on the A/D input, we would like to use a linear equation (Y=mX+b) to generate the required timer value for waveform frequencies betwoolomz. Assuming that 0V on the A/D input will correspond to 100 Hz what are the values for m and b? X = A/ inp and Y: Timer value. (2 pt.) l 99: 0&5 (554312926000 1 , I UM” UART/SCI Related 10. Write pseudo code to set up SCl-A for 7 bits data,19200 BAUD, Odd Parity and one stop bit. Assume a 25MHz external DSP crystal and that the Low Speed Clock = SYSCLOCKOUT/Z (LSPCLK = 001). Assume .set statements have been set for all required register addresses. Also assume that we will only receive characters and the receiver has been enabled as well as the SCl clock. i.e. SPlAENCLK=1 in the PCLKCRO register. (4 pts.) 3 §L,Sz/ecl<:/2~s’xw% WWW—antiw— (42m :- 431-, DE, Blaie¢(6.zsx/Dé) msz 56%? 73W 5c: Hug/VAD :o Sal ccgzooloxlio 5’25 OYZQ' , ———————o~c§7—W , 60mgan :. E WM 1 T E i W m Page 2 gunk pW) lfi / fifie pseudo code to continuously set both D/A converters to full-scale output. No nterru ts are required. (5 pt.) Q0910 / :0 c l 20 -, 45 mum fay m 91% 02/; 7t NAME .39 gauged l a 0 v1 §PIST No a 1266p aka/hp? gig; wt; 1:; f9. awe/gar X ( bgé KME/E 3 a, write 7F c SPM/XEME X £0 Zeg) My??? FFjZo 330/72ng KC; [/1 2 w] 50 gas bum")? at: E0 30/723“? / ‘ JI‘SaAla/Cffov Q? 02/? QIV/cMwC 2/ 2 Page 4 Score = 11. Write the code to poll the SCI—A receive register and echo it to GPl06:0. Assume that GPIO6:O has already been set up. Assume .set statements have been set for all required register addresses. Use the register name in your code. (3 pt.) or Check k’XiQDmeCTg—ng—sfi—fl NC; 2 W chat: cifw‘ @g l/ZAJCL U KXKZA? . om ~e i0 Q7/0630 flegmf £0 leE 12. Assuming that a ‘9' is continuously being sent out by another device to the SCI-A port, sketch what the expected 3 O-scope waveform should look like below at the SCI-A RX pin of the DSP. Note The period of the baud rate is given approximately as this width =>l |<= for timing purposes. Label all bits & voltages on your drawing below. (5 pt.) 14. A student has connected two serial DIA conve er 0 the SPI-A peripheral on their board. One of the D/As is 16 bits unsigned and the other is 24 bits unsigned. Both are rising edge triggered devices and the -CS for the 16 bit D/A has been connected to GPIOO and the other 24 bit D/A ~CS signal has been connected to GPlO1. Assume the following: i 1. The GPIO pins have been initialized as outputs. 2. SPI Clock has been enabled. 3. The Low Speed Clock (LSPCLK) has been set to its slowest rate and therefore is running much slower that the CPU internal clock. 4. The SPl BAUD has also been initialized. 5. The SPl clock phase can be left in the default power up configuration and the D/A devices should be set as slaves. 6. No interrupts are required. Polling should be used if necessary. Write the pseudo code to initialize the SPI-A peripheral to use these two devices. (3 pt. ) . . ‘00 back (Asa/HQQ g 4v .___ _o o it g m ht §EICTL 6’ Mgsréiegsmz/é :7 i. fflbkc/ v Page 3 Score = ...
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fq_sol_s10 - EEL 4744C — Dr Gugel Print Your Last Name[Z...

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