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Unformatted text preview: University of Florida ECE Dept. Page 1/2 EEL 4744 Spring 2010 Dr. Gugel Lab #5: Software Switch Debounce & Adding an 8 Bit External Output Port Purpose This lab consists of two parts. The first is to create de-bounce software for the keypad added in Lab #4 to use the keypad as a counter. The second part is to add an external port to the DSP using an 8 bit latch (74HC574). In order to add this latch, we will need to place it in the memory map of the DSP and modify the CPLD to implement the required decode equation. Both the de-bounce software and external port must be complete by the end of this lab. Part I. De-boucing a Switch via Software In Lab #4, you added a keypad to your DSP development board and wrote software to display the key pressed on your LED binary display. We will now use the same hardware as before and only modify the software to do the following: 1. Check when the "1" key is pressed on your keypad. 2. Every time the "1" key is pressed, increment a counter and display the contents of this counter on your binary display added in the last lab. 3. If a "0" is pressed, zero out the counter value. Because we are now counting the number of keystrokes, we will need to de-bounce the keypad switches. This step is necessary because when a key is pressed or released, the contacts of the switch bounce between the switch being open and closed repeatedly for several milliseconds (typically 10-50 mSec). This in turn causes your input relating to this switch to bounce between L (switch is closed and shorted to ground) and H (switch is open and pull-up resistor pulls input high). Because we only want a count of one every time a key is pressed and released, we will need to put in a short delay after the key is pressed and released to ignore the bounce. Note: In our last lab we were only interested in which key was pressed and not how many times it was pressed. Thus, if a key was pressed multiple times (switch bounce) in a few milliseconds, our display was immediately updated with this information on the first HLH transition of the bounce and all other transitions did not change or affect the display because the display now reflects the new information (key pressed). To remove switch bounce via software, we simply put in a time delay to allow the switch to settle after it has been pressed and after it has been released. Therefore, you should: 1. Test for a key pressed. 2. If pressed, delay 10-50 mSec and then update or clear counter. 3. Check when the key is released and again delay before going back to #1. Part II. Adding an 8 Bit Output Port In your parts kit you should have a 74574 latch that you will use to create an output port. See the following TI data sheet for more info: 74574 Pin-out - Check and search for a 74ABT574 and look for a DIP package. Next, add an external port in the following manner: 1. Attach a 574 to the data bus on your DSP. See our board manual for the proper XD7:0 header pins. 2. Ground the 574 ~OE pin so that the output is always enabled and never tri-stated. 3. Attach the 574 clock (CLK) input to one of your open I/O pins on your CPLD. 4. Create a decode equation in the CPLD and assign the equation output to the CPLD I/O pin you selected in #3. Note: It is recommended that you place the 574 at 0x004000 (Zone 0) in the DSP memory map. 5. Create some short assembly code to write 0x55, 0xAA, 0x0 and 0xFF to the latch in a loop and step through it using the Code Composer debugger. Very Important => Make sure no data bits are Grounded or tied to +3.3V before powering on your board. Use your multimeter and check all data bus signals wired to headers. Wiring mistakes at this point can destroy your DSP, $$ for a replacement board! Attend a workshop to pick up your CPLD from a TA and have them review your Quartus schematic before programming the CPLD in your board. Part I. In-Lab Requirements: 1. Upon entering the lab, show error-free ASM to your TA for Part I (de-bounce software). This is pre-lab material. 2. Disable your delay in your software and use the Logic State Analyzer (LSA) to trigger when the "1" is pressed. Observe the switch bounce on the LSA. Measure the duration of the bounce. 3. Next trigger the LSA when the key is released and again observe and measure the bounce. University of Florida ECE Dept. Page 2/2 EEL 4744 Spring 2010 Dr. Gugel Lab #5: Software Switch Debounce & Adding an 8 Bit External Output Port 4. Run your code with the delay and show that your program debounces the switch, counts properly, and clears when required. 5. Now use the LSA to precisely measure the duration of your delay routine: A. Select an open pin from one of the available port pins and configure it for output. B. Set the debug output pin low before a key is pressed. C. Set the output high immediately before entering the delay routine. D. Set the output pin low after leaving the delay routine. E. Add this debug output signal to your LSA and measure how long it is high once a pressed key triggers the analyzer. Part II. In-Lab Requirements: 1. Show your TA a hand drawn schematic of the latch with pin numbers and draw how it attaches to the board headers with pin numbers also denoted. 2. Show the TA a Quartus generated print-out of your schematic design or logic equations that corresponds to the decode circuitry found in the CPLD. 3. Using your voltage meter, show your TA that you can send out known patterns to your port. 4. Connect an LSA to the data bus, address bus, R/-W and the CPLD latch (decode) signal to observe a memory bus cycle. Point Breakdown: Part I. Pre-lab materials (15% Total) A. Program description, Problems Encountered (what you learned) and Applications 5% B. Flowcharts - Part I flow chart, 5% C. ASM files, 5% Part II. Pre-lab materials (25% Total) A. Program description, Problems Encountered (what you learned) and Applications 5% B. Flowcharts -Part II flow chart, 5% C. Schematic, 5% D. Logic design or equations, 5% C. ASM files, 5% Show working de-bounce switch counter (25%) Show de-bounce and a Memory Bus Cycle on the LSA (10%) Show working output port (25%) 4. You must set XINTFENCLK = 1 in the PCLKCR3 register. This enables CS0 to act as a low true data strobe. If you don’t enable this, you won’t see CS0 strobe on a write to Zone 0. 5. Finally, if you are going to use 32 bit move commands (i.e. MOV *AR0,ACC) to write to GPCMUX1, you must include the code SETC OBJMODE at the top of your program. Another option is to just use 16 bit moves as we have in previous labs and write to GPCMUX1 (lower word of the register) and then GPCMUX1+1 (upper word of the register) to access the upper 16 bits in the GPCMUX1 register. Extra Credit (5%): Add a buffer to read in the output of your latch you just added. Suggest parts are 74244, 74245 and/or a 74240. A 74574 can also be used to read the binary output and these can be external devices or one instantiated in your CPLD. Place the buffer at the same memory map address as the latch added earlier. You are responsible for finding the IC do not ask Eric Liebner for one. See and/or Additional Helpful Hints: 1. The signal used to latch data into the 74574 is derived from a CPLD output. This signal only requires the chip select from Zone 0 (xZCS0) and external read/write (xR/-W) as inputs. 2. CS0 and R/-W must be selected as outputs in GPBMUX1. The power-up default is to use these DSP pins as GPIO signals. We must over-ride this default setting and instead select CS0 and R/-W for output. 3. Similarly, we have to select external data7:0 (xD7:0) for output in GPCMUX1. These pins again default power-up as GPIO signals. ...
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This document was uploaded on 11/24/2010.

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