lab6_s10 - University of Florida Department of Electrical...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: University of Florida Department of Electrical and Computer Engineering EEL 4744 Dr. Gugel 2/24/10 - 2:43 PM Spring 2010 Lab #6: Input Buffer & Memory Expansion, Revision #2 (get your own SRAM for extra credit) Purpose This lab consists of two main topics. The first is to add an eight bit external input port to your DSP and the second is to add external SRAM memory. Part I. Input Port Expansion In your parts kit you should have a 74573 buffer that you will use to create an input port. If you have already used this part in the last lab, instantiate a new one in your CPLD. Now add the external input port in the following manner: 1. Attach the 573 to the data bus on your DSP as you did with the latch in the previous lab. 2. Create a new decode circuit in your CPLD to control the ~OE pin so that data only comes onto the data bus when you are performing a read to the Zone 0 memory space (xZCS0 data strobe). Note: If you already added an input buffer in the last lab you will need to add additional address lines for decoding such that two buffers will exist in the –CS0 memory map range. 3. Connect the buffer inputs to the outputs from the previous output latch you added in the last lab if this is your first buffer. If this is your second input buffer, connect the inputs to the GPIO lines connected to LEDs. You now should be able to write a byte out your previously added latch and then read it back via the buffer. If this is your second input buffer, you should be able read in the value sent out to your LEDs. In either or both buffer cases, use your debugger to verify this operation by stepping through code that reads these buffers. What are the available addresses that we can write and read to for accessing this external I/O (input/output) port? How many images of the input and output port exist in the DSP memory map? What would be necessary in the CPLD to perform full address decoding for the buffer? Part II. Interfacing Memory to a uP The purpose of this work is to interface a volatile memory SRAM to your DSP. This will allow us to place byte wide data in memory for future lab use. Presently, we are limited to only loading programs in internal DSP memory. We also are limited to storing data only in eternal RAM. What is the maximum amount of program and data that we can store internally in the DSP? To answer these questions, assume that in program will be placed at 0x9000 internal RAM and data at 0xA000 internal RAM per our usual previous assembly coding. To add more memory to our DSP, interface the external SRAM in the following manner: 1. Physical Device Mounting - The SRAM chip we will use is a 32K x 8 Surface Mount Device (SMD). Go to an early workshop to have this memory mounted by your TA. It is recommended that the TA solder this part on your board but if you are feeling confident, try to solder a couple pins on the device. Note: You have two available SMD footprints and thus you can choose either one for your SRAM. 2. The SRAM part number is 428-2001-5-ND from Digikey. Print out and read the first seven pages of the data sheet and bring them to class and lab. 3. Memory Map Placement - We would like to use Zone 6 in the DSP memory map for placement of this new external SRAM. This zone has a chip select (data strobe) that is called xZCS6 or CS6 for short. It is enabled from 0x100000 to 0x1FFFFF. If we just use CS6 directly as the chip enable on our SRAM, how many images of the SRAM will we have in the Zone 6 memory range? Instead, place the SRAM in the memory map starting at address 0x180000 and use full address decoding so that there is only one image of the SRAM in the memory map. What is the range of this SRAM? What address lines are required for decoding in the CPLD? Don’t forget that CS6 and the new required address lines will have to be selected as outputs as you did previously for CS0 and R/W in the last lab. 4. SRAM Signal Connection - R/~W is not required in the decode equation because it can be directly attached to the SRAM. Data lines from the DSP will go to data lines on the SRAM. Address lines on the DSP will be used the address inputs on the SRAM. ~CE on the SRAM should be connected to your decode signal created in the CPLD. ~OE on the SRAM should be tied to ~RD (XRDn) such that ~OE only goes low on a ready cycle. SRAM ~CE is therefore the only signal generated by the CPLD. Why must ~OE be high (false) on a write cycle? Hint: See the memory write timing diagram. What happens to the data lines when ~CE is false? What voltage level corresponds to ~CE being false? University of Florida Department of Electrical and Computer Engineering EEL 4744 Dr. Gugel 2/24/10 - 2:43 PM Spring 2010 Lab #6: Input Buffer & Memory Expansion, Revision #2 (get your own SRAM for extra credit) Part I. Pre-Lab/In-Lab Requirements: 5. Place one 0.1 uF cap between power and ground of the SRAM (it can be soldered in across the header pins used for wire-wrap wires) to reduce switching noise on the power supply rails. 6. Before powering your board up, make sure no data bits are grounded or tied to +3.3V before powering on the board. Use your multi-meter and check all signals wired to headers. Wiring mistakes at this point can destroy your DSP ($$)! 7. SRAM Software Testing - Once you think you have your memory functional, create the following SRAM Memory tests: Part II. Pre-Lab/In-Lab Requirements Test1. Write $AA to all locations in SRAM and then read all locations and check if $AA is present. If this passes write an $AA to your LED display, else send $EE and place the first error data value and address in memory for future viewing. Test 2. Write $55 to all locations and then read all locations to see if $55 is present. If it passes, then send $55 to your display, else write $EE and put the first error data value and address in memory for viewing. Test3. Write $00 to the first memory location, next write $01 to the next location and then $02 to the next and so on to all remaining memory locations. Read them back and verify no errors are found. If no errors are found, display $00 else display $EE and again store the first defective address and data value. Test4. Extra Credit, if you can get it to work. Load and run a program from your external SRAM.? What is the inherent problem here? How can we overcome this physical limitation? If you can get this to work, try loading your code from Lab #4 (keypad scan routine) into SRAM and run this code from your external SRAM. Note: TAs should check Tests1-3 by manually placing an erroneous value into memory (using the debugger) right before the read/verify portion of the student’s test code is executed. i.e. Have the student write the test pattern to memory, manually change a value and then have the student run the read/verify portion of the test. 1. Show your TA the data page pin-out you obtained from the web for the SRAM device. 2. Show logic equations, print-outs of Quartus circuit and/or VHDL files and hand drawn schematics to your TA. 3. Show error free ASM and list files for memory tests T1-T3. 4. Demonstrate tests T1-T3 to your TA. Let the TA manually insert a bad memory value and view the result on the display and also view the error address and data saved in a pre-determined memory location of your choice. 5. Use the LSA to observe & sketch a write cycle (view all used control lines, 4 bits of data and upper 4 bits of address) and a read cycle. Point Breakdown: Part I. Pre-lab materials (20%) Part II. Pre-lab materials (25%) Show working external latch & buffer (20%) Show working SRAM, three test cases (30%) Sketch Write & Read Cycle (5%) *Run code from external memory, extra credit (10%) *it may be possible if you have two external SRAMs to create a 16 bit wide data bus. A second SRAM can be purchased from Digikey for experimentation! 1. Show your TA a hand drawn schematic of the buffer with pin numbers and draw how it attaches to the board headers with pin numbers also denoted. 2. Show the TA a print-out of your schematic design that corresponds to the decode circuitry found in the CPLD. 3. Write a byte out your output port and then read it back in via your input port. Step this code, verify the output with a hand held meter and demonstrate this to your TA. ...
View Full Document

Ask a homework question - tutors are online