FinalExamFall07Solution

FinalExamFall07Solution - EEL 3701 — Digital Logic...

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Unformatted text preview: EEL 3701 — Digital Logic & Computer Systems ‘ Final Exam — Fall Semester 2007 Name: WU” COVER SHEET: Re-Grade Information: EEL 3701 — Digital Logic & Computer Systems Final Exam — Fall Semester 2007 Name: ‘ Remember to show ALL work here and in EVERY problem on this exam. [10%] 1. Circuit Analysis What is the logic equation for X in the given circuit? Do not simplify or transform it into an SOP or POS form. Leave the logic expression as it is after analysis. Also, draw the intermediate expression at the input to each gate. i i i i l l | - Notation reminder: A(H) is the same as A.H - Boolean expression answers must be in lexical order, i.e., /A before A, A before B, etc. i l i fl EQUATION: X = (i5*5'5‘?)'(i'5*§) '7‘ fl '5 _ ( ,2 5140515") ~ / EEL 3701 — Digital Logic & Computer Systems Final Exam — Fall Semester 2007 Name: [10%] 2. Circuit Synthesis Draw a mixed-logic circuit diagram (with the minimum number of gates) to directly implement the below equation. All inputs and the output can be of any activation-level desired. Be sure to specify the desired activation levels. Do [121 simplify this equation. You may only use gates available on 74H010 chips (shown). Use as many 74H010 chips as you need, but use the minimum number required to solve this problem. F=A*B*D + B*/C*/E + /A*C*/D fl.H;‘EDO~/Z'H 1, #,a%afi 2H—-fi W7, ’ fly» ' EEL 3701 — Digital Logic & Computer Systems Final Exam —- Fall Semester 2007 Name: [10%] 3. lm lementation of an ASM chart usin clocked S-R FFs S-R characteristic table: SR : 000 0 001 1 E 010 0 0110 0 1001 g , 101 1 x 00 110 ? (a) Given the above ASM chart, complete the following block diagram of its implementation i using the minimum number of clocked S—R flip-flops: (2%) 1 - Determine how many clocked S-R flip-flops that are needed. ° Draw in all the inputs and outputs of the combinatorial circuit. 0 Make all necessary connections to complete the block diagram (between the l _ combinatorial circuit and the clocked S—R flip—flops). Combinatorial circuit (Outputs) (Draw flipflops here.) EEL 3701 — Digital Logic & Computer Systems Final Exam — Fall Semester 2007 Name: 3. (continued) (ASM chart is repeated here for your convenience) _, S-R characteristic table: SR 00 00 01 01 10 10‘ 11 ll “Or—‘Ot—‘OHO ocw—‘OOv—‘O (b) Finish the implementation of the ASM by determining the minimum sum-of-products (MSOP) logic expressions for all the output signals: (8%) (If necessary, use the bottom/back of the previous page to do your work.) EEL 3701 — Digital Logic & Computer Systems Final Exam — Fail Semester 2007 Name: [14%] 4. Assume the below has already been run, and the code that follows in a, b, c, d, e, f, g will follow. Hand assemble the following instructions and fill in the blanks. EA is the 16-bit effective address. If there is no effective address, write none. (Use the G-CPU instruction set attached to this test). ORG $0032 ORG $0048 DataO DC.B $66 Data6 DC.B $3E I ORG $0028 ORG $0058 Datal DC.B SIX-3 Data7 DC.B $9E ORG $002A ORG $2A42 Data2 DC.B $74 Data8 DC.B $99AC ORG $0038 " Data3 DC.B EC ORG 0000 ORG :003A LDX :$OOOA X“; fflwflé" Data4 DC.B $EC LDAA #3 #9 ffljé‘“ ; ORG $0040 LDAB #37 8 afzj’ Data5 DC.B $AB SUM_AB 5 l L4;;f§’0 ADDRESS INSTRUCTION h HEX ADDRESS HEX VALUE 5 a) $0008 STAB 48,X Xrgfigxg 0008 12, EA =fflQ 3% m 0009 :0 Value stored =$28 000A 000B b) $0008 LDAA 40 424,4 $33 0008 fli of EA = 253/225 0009 23 W’35A= :45 000A Zfl 000B 0) $0008 LDX #Data8 ijflfzfifz 0008 £8 EA = $95M? 0009 fig x = {42 000A ;4 000B 01) $0008 TBA 0008 69/ EA = M £34 0009 A = 2? 000A OOOB e) $0008 LDAB Data81p/y5fZA/z 0008 a5” EA = $2,462 0009 $2 B = 72“? 000A 24 000B 3 f) $0008 BN $EF 0008 Z Z 1 EA = «70002 0009 572 PC after this OOOA instruction =f/flfl'4 000B 9;) $0008 BNE $EF 0008 2g EA 2 fflflaz 0009 t/E PC after this 000A instruction =¢dofla OOOB EEL 3701 — Digital Logic & Computer Systems Final Exam — Fall Semester 2007 Name: [14%] 5. EEPROM and SRAM (2%) Given as many 256X8 EEPROM chips and 256x8 static RAM chips as needed, design a 1024x8 memory module (with a CS) that has 512x8 of RAM at the lowest addresses and 512x8 of EEPROM at the highest addresses. The 512x8 of RAM must start at address 0 and the first address of the 512x8 of EEPROM must immediately follow the last RAM address. Add the minimum number of additional components required. Make sure the EEPROM _i_s_ NEVER enabled during a write cycle and the RAM is enabled for bo_th read and write cycle_s_. The EEPROM and SRAM devices have active low CS and the SRAM devices have a W control signal. a) What is the address range for each of the memory components (in binary and in hex)? 664’}??? ~ WWW 9W Jet ////A //// $200 #30: SRAM 55449713 04 Marmara $1,. mg: 1/11 #70 (2 «a? as: EEPROMég’ezw *6; /0Aflflfl46%& - /4////¢//// Azw— #255 (12%) ggfimfirjfi HAMMAMM 4/4 ///¢//// $3M viii/4‘ b) Design the required memory device below. Make sure you show the memory module’s inputs and outputs and all the individual memory component devices. Use labels instead of wires in the design. EEL 3701 — Digital Logic & Computer Systems Final Exam — Fall Semester 2007 Name: [15%] 6. HAND Assembly The following program finds all occurrences of $37 in a table with an $FF end of table marker and replaces them with $AA. it uses the G-CPU instruction set attached to this test. Hand assemble the program in the space given. Address Data (Hex) Program fflfiéf y/ga 10 ORG $100 &/a / 37 Table DC.B $10,$37,$CC,$37,$15 [5 EOT DC.B , $FF 4/93 37 v EQU $AA OLD EQU $C8 ' 5&7“ FF ORG $200 TRT LDX #Table fiTWf &269& 0, ' LOOP LDAB EOT w COMB I . LDAA 03X Md? Mg 0 ’ SUM_BA fl M 39" fl BEQ QUIT LDAA 0X 52.2%; 13 r DAB #OLD 423433 #6? 935/? Q Q} UM_BA / 2; 3 a0 . BNE NOSW yz/a " fl ‘ LDAA #NEW pay/4 2 ‘ STAA 0,X } OSW INX 02am 0C 1 ENE LOOP l QUIT BEQ QUIT awe“ flMF 6’ : Z/fl 2 m; M" m“ A, E 4%,!) 14* IVE/u LP/f/fffi‘fl/f flit/l5” = - a flay/é m) E5794” (’2’)‘ fl/Qfét/ will 2Q / 27W m dig-4% 2. ' « / ’— a 7 599% 1 E 54’Q Ayw/ EEL 3701 — Digital Logic & Computer Systems Final Exam — Fall Semester 2007 Name: [15%] 7. GCPU Assembly Programming (Use the G-CPU instruction set attached to this test) Write an entire G-CPU program to copy all the positive values in a table called TABl (beginning at address $3000) to another table called TAB2 (beginning at address $7000). l TABl has 200 l-byte values already in memory. There is a l6-KB ROM for your program, starting at address 0 and a 32—KB SRAM, starting at $4000 for data. Be sure to initialize all necessary values, variables, etc., i.e., assume no initializations are done for you. Be sure to properly terminate the program (so it does not execute past the end of your program). Use labels instead of numbers in assembl instructions wherever ossible. i g 3 l i l i l l l l l ‘3“ r r I. Vs I. EEL 3701 — Digital Logic & Computer Systems Final Exam — Fall Semester 2007 Name: [12%] 8. GCPU Instruction Design (See the G-CPU Next State Table attached to this test) We want to implement a new instruction for the GCPU. The new instruction will be denoted as SBAM addr. It added the content of register B to register A (like SUMflBA). But, it also stores the result into memory at location “addr”. The new opcode for this instruction will be - % designated as $32 and the next state available in the Controller’s ASM is $34. Show the additional states required to implement this new instruction in the Controller’s ASM below and show all controller output signals that must be true in each new state for this new instruction: Assume: R/-W is True for Read and False for Write. Control Signals: PC_INC, PC_LDflUpper, PC_LD_Lower, MAR_INC, MAR_LD_Upper, MAR_LD_Lower, X_lNC, X_LD_Upper, X_LD_Lower, Y_INC, Y_LD_Upper, Y_LD_Lower, IR_LD, Rl-W, ADDR_SEL1 :0, XD_LD, YD_LD Notelz The controller output signals are also shown in the G CPU Block Diagram for reference. Fill in the ASM for SBAM $addr (12 pts.): State = 000000 IR_LD = T R/-W = T 000001 R/-W = T 1/? = $12 Existing G CPU instructions SBAM $addr Opcode = $32 , 4/4” ; M/f/é- 4}. ma” .» flfi/r 50/ ‘ ‘ flaw =70 KAI/Va 10 EEL 3701 — Digital Logic & Computer Systems Final Exam — Fall Semester 2007 Name: GCPU Instructions litata Movement Instructions: 'ansl'er A to B (inherent addressinu' - "at‘rsl'er B to A (inherent addressing) LDAA #data ad A with immediate data (immediate addr.) ad B with immediate data (immediate addr.) Load A with data from mentor;r location addr S (extended address] no) |6 bit address Load [3 with data from me in ory location ad dr 5 l lextended addressinn] 2 l6 bit address Store data in A to memory location addr (extended 5 addressing] addressirm) Load X with immediate data [immediate ader 5‘ Load Y with immediate data (immediate addrz') Load X with data l’rom memory location addr. (extended addressi no) to hit addr Load Y with data item memory location add 1'. (extended add ressi no) 8 bit Load A with data l'tom memory location pointed to dis Jlacement bv X + dd {indexed addressing) Load A with data from menion location pointed to dis nlacement bv Y + dd (indexed addressing] Load B with data from mentor)r location pointed to dis alacement bv X + dd [indexed add ressirmi - 8 bit Load B with data from n‘temory location pointed to dis Jlacement be ‘r’ 4- dd (indexed addressinel “ STAA dd,X 8 bit Store data in A to memory location pointed to by X dis Jlacement + dd {indexed addressinu] u S bit Store data in A to memory location pointed to by Y 2 dis Jlacemenl + dd 1‘ indexed addressinL-l STAB ddx 8 bit Store data in B to memortr location pointed to by X + disalacement dd [indexed addressinn) STAB dd,Y Shit Store data in B to mentor)r location pointed to by Y + dis Jlacement dd (indexoi arlrlressinnJ l> none l 1 |.-\ i l u: i m- l Branch il‘ A - 0. i.e.. Z Flag — l (absolute addressina) Branch if A :r 0. Le. Z Flag — 0 (absolute addressina) Branch it .A\ is negative. i.e.. N Flag — l [absolute addressi not Branch ii' A is positive iorzcro'i. i.e.. N Flag - O [absol ute addressinu) -- S mial Notes i. Z [lag and N [tag are only setantl clearod by the router ' ' 2. A branch is accomplished by moving the operand addres The upper ber of the PC remains unch- l aliera branch. 3. The Branch instructions use abwlrrteatltlressing where only the low byte of the address is used as an operand. it" the branch condition is met. the high byte ol'the PC is unchanged and the low ) byte takes the value of the operand [ader]. “F'I‘rA. ( dr’ to the lower byte ol'the PC. l i l l l l l ll EEL 3701 — Digital Logic & Computer Systems Final Exam — Fall Semester 2007 Name: GCPU Block Diagram Bi~dixwlinml IXIIH Bus - 9° (5 IR- Ill IRS“) ( H‘ Rt-gislel' M UNA i\-| UXB Conl roller .:\l.l! 7. Flag N Flag l’C_lN(~ I>c_LD I LIILI 7. Flag MARJNC MAR_LD I'LlV-‘LII N Flag X_I:\’(‘ .\’_ LD (UELJ \’_IN(' ‘r'_, LD (Ll! LII lR_Ll) Ri—W J'\ DDR_SEL | :D MU KC 3 5 (Reset mu shuwu duo l0 5])“ CL" CDHSU'EII'MS] XD_LD YD_LD i iu-w l _ Address Bus ‘.\' Reg Block M“) Mux {I 16 3 Y Reg Block S SO . I Nola: PC. MAK X. Y oulpuls are 16 bus Mum “HZ” X Reg Blu'k —— X displacement Reg + X Reg (l-li'L) Y Reg Blcck — Y clifiplncemenl Reg + Y Reg (l-lx'LJ Rl£('.i.-'\ Bus to OUTPU'I' Bus RliUB Bus lo OUTPUT Bus complement of Rl-LGA Bus 10 OUTPUT Bus bit \\'150 .-'\Nl) RIF. \JRIEGB Bus to OUTPUT Bus hil Wise ()R Rl-IG:-\.-"Rli(il3 Bus. [0 OU'l'I’U’l' Bus sum ui' RliGA Bus& Rl-ZGB Bus lo OU'l'l’U'l' Bus shil'l Rli(.i.-'\ Bus loll one hil lo OU'I'I’U'l' Bus shill Rl-IfiA Bus right one hit 10 OUTPUT iwilhnul signcxlcusiom Bus Selected as Input to REGA/REGB — REGA Out )ul' Bus -- .- Bus 12 EEL 3701 — Digital Logic & Computer Systems Final Exam — Fall Semester 2007 Name: Partial GCPU Next State Table m Max Select REG AD D R XX Diap INC SEL I MAR Luadiu-z firm "3 ‘L PC — II ' IR R LI) LU LI) LD 0 5...!) [115.11 .. . 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FinalExamFall07Solution - EEL 3701 — Digital Logic...

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