FinalExamFall08 - EEL 3701 Digital Logic & Computer Systems...

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EEL 3701 – Digital Logic & Computer Systems Final Exam – Fall Semester 2008 Name:_________________________________ 1 COVER SHEET: Prob. Points: 1 (8) 2 (10) 3 (12) 4 (10) 5 (12) 6 (12) 7 (12) 8 (12) 9 (12) Total: Re-Grade Information: _________________________________________________________ _________________________________________________________ _________________________________________________________ _________________________________________________________ _________________________________________________________ _________________________________________________________ _________________________________________________________ _________________________________________________________ _________________________________________________________ _________________________________________________________ _________________________________________________________ _________________________________________________________ _________________________________________________________ _________________________________________________________ _________________________________________________________ _________________________________________________________ _________________________________________________________ _________________________________________________________ _________________________________________________________ _________________________________________________________ _________________________________________________________ _________________________________________________________ _________________________________________________________ _________________________________________________________ _________________________________________________________ (100)
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EEL 3701 – Digital Logic & Computer Systems Final Exam – Fall Semester 2008 Name:_________________________________ 2 Remember to show ALL work here and in EVERY problem on this exam. [8%] 1. Circuit Analysis NOTE: To obtain partial credit , label intermediate signals. (a) Analyze the above circuit and derive the logic equation for Z1. (4 pts.) Do not reduce or transform the logic expression (except for the “double inversions”). Put the logic equation for the Z1 “as it is”. Z1 = (b) Complete the following VOLTAGE table for Z2. Use “L” for low voltage, “H” for high voltage, “(Z)” for high impedance. Also use “X” for don’t cares (and wild cards) to reduce the table size. (4 pts.) A.L B.H C.L D.H Z2.H Z1.L This is a tri-state buffer. A B C D Z2
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Final Exam – Fall Semester 2008 Name:_________________________________ 3 [10%] 2. You have five total gates available from these two chips, a single 74’00 and a single 74’02 (i.e., 5 total gates from any combination of 74’00 and 74’02 gates). Draw a mixed-logic circuit diagram for the below equation using only the available gates . Do not simplify this equation. Specify the desired activation levels to accomplish the required design and add appropriate pin numbers
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FinalExamFall08 - EEL 3701 Digital Logic & Computer Systems...

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