This preview shows pages 1–3. Sign up to view the full content.
This preview has intentionally blurred sections. Sign up to view the full version.View Full Document
Unformatted text preview: 525.412 Computer Architecture Assignment 4 Solutions 4.15 Repeat Exercise 4.5 for the 2- and 3-bus microarchitectures. Solution Exercise 4.5 called for the concrete RTN steps and control sequences for the not instruction implemented in the 1-bus architecture. The abstract RTN for the not instruction is presented on page 63 of the textbook: not (:=op=24) R[ra] R[rc]. Here is concrete RTN for this instruction on the 2-bus architecture: Step Concrete RTN Control Sequence T0-T2 Instruction Fetch (see page 169 of the text) T3 R[ra] R[rc] Grc,R out ,NOT,R in ,S ra ,End And here is concrete RTN for this instruction on the 3-bus architecture: Step Concrete RTN Control Sequence T0-T1 Instruction Fetch (see page 169 of the text) T2 R[ra] R[rc] GBrc,RB out ,NOT,R in ,S ra ,End 1 4.18 Modify the hardwired control unit design shown in Figure 4.12 and Figure 4.15 to support the Rst and modified Run signals described in Section 4.7.2. You will also need to modify the register file, shown in Figure 4.4. Asssume that the Rst signal is asynchronous. Solution Some of the details of Figure 4.12 are to be found in Figure 4.14. The original version of the abstract RTN for Run and Strt can be found on page 175: instruction interpretation:=( Run Strt (Run 1;instruction interpretation): Run (IR M[PC]:PC...
View Full Document
This note was uploaded on 11/25/2010 for the course ECE 525.412 taught by Professor Charlesb.cameron during the Spring '10 term at Johns Hopkins.
- Spring '10
- Computer Architecture